157 lines
1.9 KiB
Plaintext
157 lines
1.9 KiB
Plaintext
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The STM32 Cortex-M4 instruction set
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PM0214
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52/262
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PM0214 Rev 10
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LDREXB
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Rt, [Rn]
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Load register exclusive with
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byte
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—
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3.4.8 on page 79
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LDREXH
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Rt, [Rn]
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Load register exclusive with
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halfword
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—
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3.4.8 on page 79
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LDRH,
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LDRHT
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Rt, [Rn, #offset]
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Load register with halfword
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—
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3.4 on page 69
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LDRSB,
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LDRSBT
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Rt, [Rn, #offset]
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Load register with signed byte
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—
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3.4 on page 69
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LDRSH,
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LDRSHT
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Rt, [Rn, #offset]
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Load register with signed
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halfword
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—
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3.4 on page 69
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LDRT
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Rt, [Rn, #offset]
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Load register with word
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—
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3.4 on page 69
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LSL, LSLS
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Rd, Rm, <Rs|#n>
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Logical shift left
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N,Z,C
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3.5.3 on page 86
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LSR, LSRS
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Rd, Rm, <Rs|#n>
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Logical shift right
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N,Z,C
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3.5.3 on page 86
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MLA
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Rd, Rn, Rm, Ra
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Multiply with accumulate, 32-
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bit result
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—
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3.6.1 on page 110
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MLS
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Rd, Rn, Rm, Ra
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Multiply and subtract, 32-bit
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result
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—
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3.6.1 on page 110
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MOV, MOVS
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Rd, Op2
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Move
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N,Z,C
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3.5.6 on page 89
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MOVT
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Rd, #imm16
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Move top
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—
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3.5.7 on page 91
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MOVW,
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MOV
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Rd, #imm16
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Move 16-bit constant
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N,Z,C
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3.5.6 on page 89
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MRS
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Rd, spec_reg
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Move from special register to
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general register
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—
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3.11.6 on page 186
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MSR
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spec_reg, Rm
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Move from general register to
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special register
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N,Z,C,V 3.11.7 on page 187
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MUL, MULS
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{Rd,} Rn, Rm
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Multiply, 32-bit result
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N,Z
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3.6.1 on page 110
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MVN, MVNS
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Rd, Op2
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Move NOT
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N,Z,C
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3.5.6 on page 89
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NOP
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—
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No operation
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—
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3.11.8 on page 188
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ORN, ORNS
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{Rd,} Rn, Op2
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Logical OR NOT
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N,Z,C
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3.5.2 on page 85
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ORR, ORRS
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{Rd,} Rn, Op2
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Logical OR
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N,Z,C
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3.5.2 on page 85
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PKHTB,
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PKHBT
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{Rd,} Rn, Rm, Op2
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Pack Halfword
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-
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3.8.1 on page 135
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POP
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reglist
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Pop registers from stack
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—
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3.4.7 on page 78
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PUSH
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reglist
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Push registers onto stack
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—
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3.4.7 on page 78
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QADD
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{Rd,} Rn, Rm
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Saturating double and add
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-
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3.7.3 on page 128
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QADD16
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{Rd,} Rn, Rm
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Saturating add 16
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-
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3.7.3 on page 128
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QADD8
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{Rd,} Rn, Rm
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Saturating add 8
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-
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3.7.3 on page 128
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QASX
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{Rd,} Rn, Rm
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Saturating add and subtract
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with exchange
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-
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3.7.4 on page 129
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Table 21. Cortex-M4 instructions (continued)
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Mnemonic
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Operands
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Brief description
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Flags
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Page
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