38 lines
2.4 KiB
Markdown
38 lines
2.4 KiB
Markdown
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来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 51
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The STM32 Cortex-M4 instruction set
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**Table 21. Cortex-M4 instructions (continued)**
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| Mnemonic | Operands | Brief description | Flags | Page |
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|----------|----------|-------------------|-------|------|
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| AND, ANDS | {Rd,} Rn, Op2 | Logical AND | N,Z,C | 3.5.2 on page 85 |
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| ASR, ASRS | Rd, Rm, <Rs|#n> | Arithmetic shift right | N,Z,C | 3.5.3 on page 86 |
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| B | label | Branch | — | 3.9.5 on page 142 |
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| BFC | Rd, #lsb, #width | Bit field clear | — | 3.9.1 on page 139 |
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| BFI | Rd, Rn, #lsb, #width | Bit field insert | — | 3.9.1 on page 139 |
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| BIC, BICS | {Rd,} Rn, Op2 | Bit clear | N,Z,C | 3.5.2 on page 85 |
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| BKPT | #imm | Breakpoint | — | 3.11.1 on page 181 |
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| BL | label | Branch with link | — | 3.9.5 on page 142 |
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| BLX | Rm | Branch indirect with link | — | 3.9.5 on page 142 |
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| BX | Rm | Branch indirect | — | 3.9.5 on page 142 |
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| CBNZ | Rn, label | Compare and branch if non zero | — | 3.9.6 on page 144 |
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| CBZ | Rn, label | Compare and branch if zero | — | 3.9.6 on page 144 |
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| CLREX | — | Clear exclusive | — | 3.4.9 on page 80 |
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| CLZ | Rd, Rm | Count leading zeros | — | 3.5.4 on page 87 |
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| CMN | Rn, Op2 | Compare negative | N,Z,C,V | 3.5.5 on page 88 |
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| CMP | Rn, Op2 | Compare | N,Z,C,V | 3.5.5 on page 88 |
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| CPSID | iflags | Change processor state, disable interrupts | — | 3.11.2 on page 182 |
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| CPSIE | iflags | Change processor state, enable interrupts | — | 3.11.2 on page 182 |
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| DMB | — | Data memory barrier | — | 3.11.4 on page 184 |
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| DSB | — | Data synchronization barrier | — | 3.11.4 on page 184 |
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| EOR, EORS | {Rd,} Rn, Op2 | Exclusive OR | N,Z,C | 3.5.2 on page 85 |
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| ISB | — | Instruction synchronization barrier | — | 3.11.5 on page 185 |
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| IT | — | If-then condition block | — | 3.9.7 on page 145 |
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| LDM | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
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| LDMDB, LDMEA | Rn{!}, reglist | Load multiple registers, decrement before | — | 3.4.6 on page 76 |
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| LDMFD, LDMIA | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
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| LDR | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
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| LDRB, LDRBT | Rt, [Rn, #offset] | Load register with byte | — | 3.4 on page 69 |
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| LDRD | Rt, Rt2, [Rn, #offset] | Load register with two bytes | — | 3.4.2 on page 71 |
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| LDREX | Rt, [Rn, #offset] | Load register exclusive | — | 3.4.8 on page 79 |
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