test: PDF洗MD v5 第二批测试 — 12页（含寄存器/代码/位域表）

新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
2026-06-10 16:03:04 +08:00
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 2
+
+| 章节号 | 标题 | 页码 |
+|--------|------|------|
+| 1 | About this document | 12 |
+| 1.1 | Typographical conventions | 12 |
+| 1.2 | List of abbreviations for registers | 12 |
+| 1.3 | About the STM32 Cortex-M4 processor and core peripherals | 13 |
+| 1.3.1 | System level interface | 14 |
+| 1.3.2 | Integrated configurable debug | 14 |
+| 1.3.3 | Cortex-M4 processor features and benefits summary | 15 |
+| 1.3.4 | Cortex-M4 core peripherals | 16 |
+| 2 | The Cortex-M4 processor | 17 |
+| 2.1 | Programmers model | 17 |
+| 2.1.1 | Processor mode and privilege levels for software execution | 17 |
+| 2.1.2 | Stacks | 17 |
+| 2.1.3 | Core registers | 18 |
+| 2.1.4 | Exceptions and interrupts | 26 |
+| 2.1.5 | Data types | 26 |
+| 2.1.6 | The Cortex microcontroller software interface standard (CMSIS) | 26 |
+| 2.2 | Memory model | 28 |
+| 2.2.1 | Memory regions, types and attributes | 29 |
+| 2.2.2 | Memory system ordering of memory accesses | 29 |
+| 2.2.3 | Behavior of memory accesses | 30 |
+| 2.2.4 | Software ordering of memory accesses | 31 |
+| 2.2.5 | Bit-banding | 32 |
+| 2.2.6 | Memory endianness | 34 |
+| 2.2.7 | Synchronization primitives | 34 |
+| 2.2.8 | Programming hints for the synchronization primitives | 36 |
+| 2.3 | Exception model | 37 |
+| 2.3.1 | Exception states | 37 |
+| 2.3.2 | Exception types | 37 |
+| 2.3.3 | Exception handlers | 39 |
+| 2.3.4 | Vector table | 40 |
+| 2.3.5 | Exception priorities | 41 |
+| 2.3.6 | Interrupt priority grouping | 41 |
+| 2.3.7 | Exception entry and return | 42 |
+
+> 原始图片：imgs/page_2_*.png（无图则注明无图）
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 13
+
+1.3
+About the STM32 Cortex-M4 processor and core peripherals
+
+The Cortex-M4 processor is a high performance 32-bit processor designed for the
+microcontroller market. It offers significant benefits to developers, including:
+•
+outstanding processing performance combined with fast interrupt handling
+•
+enhanced system debug with extensive breakpoint and trace capabilities
+•
+efficient processor core, system and memories
+•
+ultra-low power consumption with integrated sleep modes
+•
+platform security robustness, with integrated memory protection unit (MPU).
+The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage
+pipeline Harvard architecture, making it ideal for demanding embedded applications. The
+processor delivers exceptional power efficiency through an efficient instruction set and
+extensively optimized design, providing high-end processing hardware including IEEE754-
+compliant single-precision floating-point computation, a range of single-cycle and SIMD
+multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated
+hardware division.
+
+**Figure 1. STM32 Cortex-M4 implementation**
+
+![图 1](imgs/page_13_fig_1.png)
+
+Embedded
+Trace Macrocell
+NVIC
+Debug
+access
+port
+Memory
+protection unit
+Serial
+wire
+viewer
+Bus matrix
+Code
+interface
+SRAM and
+peripheral interface
+Data
+watchpoints
+Flash
+patch
+Cortex-M4
+processor
+FPU
+Processor
+core
+
+> 原始图片：imgs/page_13_fig_1.png
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 12
+
+1
+About this document
+
+This document provides the information required for application and system-level software
+development. It does not provide information on debug components, features, or operation.
+This material is for microcontroller software and hardware engineers, including those who
+have no experience of Arm products.
+This document applies to Arm®(a)-based devices.
+
+1.1
+Typographical conventions
+
+The typographical conventions used in this document are:
+
+1.2
+List of abbreviations for registers
+
+The following abbreviations are used in register descriptions:
+
+a.
+Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
+italic
+Highlights important notes, introduces special terminology, denotes
+internal cross-references, and citations.
+< and >
+Enclose replaceable terms for assembler syntax where they appear in
+code or code fragments. For example:
+LDRSB<cond> <Rt>, [<Rn>, #<offset>]
+bold
+Highlights interface elements, such as menu names. Denotes signal
+names. Also used for terms in descriptive lists, where appropriate.
+monospace
+Denotes text that you can enter at the keyboard, such as commands,
+file and program names, and source code.
+monospace
+Denotes a permitted abbreviation for a command or option. You can
+enter the underlined text instead of the full command or option name.
+monospace italic
+Denotes arguments to monospace text where the argument is to be
+replaced by a specific value.
+monospace bold
+Denotes language keywords when used outside example code.
+read/write (rw)
+Software can read and write to these bits.
+read-only (r)
+Software can only read these bits.
+write-only (w)
+Software can only write to this bit.
+Reading the bit returns the reset value.
+read/clear (rc_w1)
+Software can read as well as clear this bit by writing 1.
+Writing '0' has no effect on the bit value.
+read/clear (rc_w0)
+Software can read as well as clear this bit by writing 0.
+Writing '1' has no effect on the bit value.
+toggle (t)
+Software can only toggle this bit by writing '1'. Writing '0' has no effect.
+Reserved (Res.)
+Reserved bit, must be kept at reset value.
+
+> 原始图片：imgs/page_12_*.png（无图则注明无图）
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 18
+
+2.1.3
+Core registers
+
+**Figure 2. Processor core registers**
+
+![图 2](imgs/page_18_fig_2.png)
+
+**Table 2. Summary of processor mode, execution privilege level, and stack usage**
+
+| Processor mode | Used to execute | Privilege level for software execution | Stack used |
+|----------------|-----------------|---------------------------------------|------------|
+| Thread | Applications | Privileged or unprivileged (1) | Main stack or process stack (1) |
+| Handler | Exception handlers | Always privileged | Main stack |
+
+1. See CONTROL register on page 25.
+
+**Table 3. Core register set summary**
+
+| Name | Type (1) | Required privilege (2) | Reset value | Description |
+|------|----------|------------------------|-------------|-------------|
+| R0-R12 | read-write | Either | Unknown | General-purpose registers on page 19 |
+| MSP | read-write | Privileged | See description | Stack pointer on page 19 |
+| PSP | read-write | Either | Unknown | Stack pointer on page 19 |
+| LR | read-write | Either | 0xFFFFFFFF | Link register on page 19 |
+| PC | read-write | Either | See description | Program counter on page 19 |
+
+> 原始图片：imgs/page_18_fig_2.png
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 20
+
+These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is
+shown in Figure 3 and Figure 4.
+
+**Figure 3. APSR, IPSR and EPSR bit assignment**
+
+![图 3](imgs/page_20_fig_3.png)
+
+**Figure 4. PSR bit assignment**
+
+![图 4](imgs/page_20_fig_4.png)
+
+Access these registers individually or as a combination of any two or all three registers,
+using the register name as an argument to the MSR or MRS instructions. For example:
+•
+Read all of the registers using PSR with the MRS instruction.
+•
+Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.
+The PSR combinations and attributes are:
+
+See the instruction descriptions MRS on page 186 and MSR on page 187 for more
+information about how to access the program status registers.
+
+**Table 4. PSR register combinations**
+
+| Register | Type | Combination |
+|----------|------|-------------|
+| PSR | read-write(1), (2) | APSR, EPSR, and IPSR |
+| IEPSR | read-only | EPSR and IPSR |
+| IAPSR | read-write(1) | APSR and IPSR |
+| EAPSR | read-write(2) | APSR and EPSR |
+
+1. The processor ignores writes to the IPSR bits.
+2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
+
+| 25 24 23 | Reserved | ISR_NUMBER | 31 30 29 28 27 | N Z C V | 0 | Reserved |
+|----------|----------|------------|----------------|---------|---|----------|
+| 26 | Reserved | | 16 15 | ICI/IT | ICI/IT | T | Q |
+| 8 | 19 | 20 | GE[3:0] | Reserved | | |
+
+> 原始图片：imgs/page_20_fig_3.png, imgs/page_20_fig_4.png
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 21
+
+Application program status register
+
+The APSR contains the current state of the condition flags from previous instruction
+executions. See the register summary in Table 3 on page 18 for its attributes. The bit
+assignment is:
+
+**Table 5. APSR bit definitions**
+
+| Bits | Description |
+|------|-------------|
+| Bit 31 | N: Negative or less than flag:<br>0: Operation result was positive, zero, greater than, or equal<br>1: Operation result was negative or less than. |
+| Bit 30 | Z: Zero flag:<br>0: Operation result was not zero<br>1: Operation result was zero. |
+| Bit 29 | C: Carry or borrow flag:<br>0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit<br>1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit. |
+| Bit 28 | V: Overflow flag:<br>0: Operation did not result in an overflow<br>1: Operation resulted in an overflow. |
+| Bit 27 | Q: DSP overflow and saturation flag: Sticky saturation flag.<br>0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero<br>1: Indicates when an SSAT or USAT instruction results in saturation, or indicates a DSP overflow.<br>This bit is cleared to zero by software using an MRS instruction. |
+| Bits 26:20 | Reserved. |
+| Bits 19:16 | GE[3:0]: Greater than or Equal flags. See SEL on page 105 for more information. |
+| Bits 15:0 | Reserved. |
+
+> 原始图片：imgs/page_21_*.png（无图则注明无图）
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 51
+
+The STM32 Cortex-M4 instruction set
+
+**Table 21. Cortex-M4 instructions (continued)**
+
+| Mnemonic | Operands | Brief description | Flags | Page |
+|----------|----------|-------------------|-------|------|
+| AND, ANDS | {Rd,} Rn, Op2 | Logical AND | N,Z,C | 3.5.2 on page 85 |
+| ASR, ASRS | Rd, Rm, <Rs\|#n> | Arithmetic shift right | N,Z,C | 3.5.3 on page 86 |
+| B | label | Branch | — | 3.9.5 on page 142 |
+| BFC | Rd, #lsb, #width | Bit field clear | — | 3.9.1 on page 139 |
+| BFI | Rd, Rn, #lsb, #width | Bit field insert | — | 3.9.1 on page 139 |
+| BIC, BICS | {Rd,} Rn, Op2 | Bit clear | N,Z,C | 3.5.2 on page 85 |
+| BKPT | #imm | Breakpoint | — | 3.11.1 on page 181 |
+| BL | label | Branch with link | — | 3.9.5 on page 142 |
+| BLX | Rm | Branch indirect with link | — | 3.9.5 on page 142 |
+| BX | Rm | Branch indirect | — | 3.9.5 on page 142 |
+| CBNZ | Rn, label | Compare and branch if non zero | — | 3.9.6 on page 144 |
+| CBZ | Rn, label | Compare and branch if zero | — | 3.9.6 on page 144 |
+| CLREX | — | Clear exclusive | — | 3.4.9 on page 80 |
+| CLZ | Rd, Rm | Count leading zeros | — | 3.5.4 on page 87 |
+| CMN | Rn, Op2 | Compare negative | N,Z,C,V | 3.5.5 on page 88 |
+| CMP | Rn, Op2 | Compare | N,Z,C,V | 3.5.5 on page 88 |
+| CPSID | iflags | Change processor state, disable interrupts | — | 3.11.2 on page 182 |
+| CPSIE | iflags | Change processor state, enable interrupts | — | 3.11.2 on page 182 |
+| DMB | — | Data memory barrier | — | 3.11.4 on page 184 |
+| DSB | — | Data synchronization barrier | — | 3.11.4 on page 184 |
+| EOR, EORS | {Rd,} Rn, Op2 | Exclusive OR | N,Z,C | 3.5.2 on page 85 |
+| ISB | — | Instruction synchronization barrier | — | 3.11.5 on page 185 |
+| IT | — | If-then condition block | — | 3.9.7 on page 145 |
+| LDM | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
+| LDMDB, LDMEA | Rn{!}, reglist | Load multiple registers, decrement before | — | 3.4.6 on page 76 |
+| LDMFD, LDMIA | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
+| LDR | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
+| LDRB, LDRBT | Rt, [Rn, #offset] | Load register with byte | — | 3.4 on page 69 |
+| LDRD | Rt, Rt2, [Rn, #offset] | Load register with two bytes | — | 3.4.2 on page 71 |
+| LDREX | Rt, [Rn, #offset] | Load register exclusive | — | 3.4.8 on page 79 |
+| LDRH, LDRHT | Rt, [Rn, #offset] | Load register with halfword | — | 3.4 on page 69 |
+| LDRSB, LDRSBT | Rt, [Rn, #offset] | Load register with signed byte | — | 3.4 on page 69 |
+| LDRSH, LDRSHT | Rt, [Rn, #offset] | Load register with signed halfword | — | 3.4 on page 69 |
+| LDRT | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
+| LSL, LSLS | Rd, Rm, <Rs\|#n> | Logical shift left | N,Z,C | 3.5.3 on page 86 |
+| LSR, LSRS | Rd, Rm, <Rs\|#n> | Logical shift right | N,Z,C | 3.5.3 on page 86 |
+| MLA | Rd, Rn, Rm, Ra | Multiply with accumulate, 32-bit result | — | 3.6.1 on page 110 |
+| MLS | Rd, Rn, Rm, Ra | Multiply and subtract, 32-bit result | — | 3.6.1 on page 110 |
+| MOV, MOVS | Rd, Op2 | Move | N,Z,C | 3.5.6 on page 89 |
+| MOVT | Rd, #imm16 | Move top | — | 3.5.7 on page 91 |
+| MOVW, MOV | Rd, #imm16 | Move 16-bit constant | N,Z,C | 3.5.6 on page 89 |
+| MRS | Rd, spec_reg | Move from special register to general register | — | 3.11.6 on page 186 |
+| MSR | spec_reg, Rm | Move from general register to special register | N,Z,C,V | 3.11.7 on page 187 |
+| MUL, MULS | {Rd,} Rn, Rm | Multiply, 32-bit result | N,Z | 3.6.1 on page 110 |
+| MVN, MVNS | Rd, Op2 | Move NOT | N,Z,C | 3.5.6 on page 89 |
+| NOP | — | No operation | — | 3.11.8 on page 188 |
+| ORN, ORNS | {Rd,} Rn, Op2 | Logical OR NOT | N,Z,C | 3.5.2 on page 85 |
+| ORR, ORRS | {Rd,} Rn, Op2 | Logical OR | N,Z,C | 3.5.2 on page 85 |
+| PKHTB, PKHBT | {Rd,} Rn, Rm, Op2 | Pack Halfword | — | 3.8.1 on page 135 |
+| POP | reglist | Pop registers from stack | — | 3.4.7 on page 78 |
+| PUSH | reglist | Push registers onto stack | — | 3.4.7 on page 78 |
+| QADD | {Rd,} Rn, Rm | Saturating double and add | — | 3.7.3 on page 128 |
+| QADD16 | {Rd,} Rn, Rm | Saturating add 16 | — | 3.7.3 on page 128 |
+| QADD8 | {Rd,} Rn, Rm | Saturating add 8 | — | 3.7.3 on page 128 |
+| QASX | {Rd,} Rn, Rm | Saturating add and subtract with exchange | — | 3.7.4 on page 129 |
+
+> 原始图片：imgs/page_51_*.png（无图则注明无图）
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 52
+
+The STM32 Cortex-M4 instruction set
+
+| Mnemonic | Operands | Brief description | Flags | Page |
+|----------|----------|-------------------|-------|------|
+| LDREXB | Rt, [Rn] | Load register exclusive with byte | — | 3.4.8 on page 79 |
+| LDREXH | Rt, [Rn] | Load register exclusive with halfword | — | 3.4.8 on page 79 |
+| LDRH, LDRHT | Rt, [Rn, #offset] | Load register with halfword | — | 3.4 on page 69 |
+| LDRSB, LDRSBT | Rt, [Rn, #offset] | Load register with signed byte | — | 3.4 on page 69 |
+| LDRSH, LDRSHT | Rt, [Rn, #offset] | Load register with signed halfword | — | 3.4 on page 69 |
+| LDRT | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
+| LSL, LSLS | Rd, Rm, <Rs\|#n> | Logical shift left | N,Z,C | 3.5.3 on page 86 |
+| LSR, LSRS | Rd, Rm, <Rs\|#n> | Logical shift right | N,Z,C | 3.5.3 on page 86 |
+| MLA | Rd, Rn, Rm, Ra | Multiply with accumulate, 32-bit result | — | 3.6.1 on page 110 |
+| MLS | Rd, Rn, Rm, Ra | Multiply and subtract, 32-bit result | — | 3.6.1 on page 110 |
+| MOV, MOVS | Rd, Op2 | Move | N,Z,C | 3.5.6 on page 89 |
+| MOVT | Rd, #imm16 | Move top | — | 3.5.7 on page 91 |
+| MOVW, MOV | Rd, #imm16 | Move 16-bit constant | N,Z,C | 3.5.6 on page 89 |
+| MRS | Rd, spec_reg | Move from special register to general register | — | 3.11.6 on page 186 |
+| MSR | spec_reg, Rm | Move from general register to special register | N,Z,C,V | 3.11.7 on page 187 |
+| MUL, MULS | {Rd,} Rn, Rm | Multiply, 32-bit result | N,Z | 3.6.1 on page 110 |
+| MVN, MVNS | Rd, Op2 | Move NOT | N,Z,C | 3.5.6 on page 89 |
+| NOP | — | No operation | — | 3.11.8 on page 188 |
+| ORN, ORNS | {Rd,} Rn, Op2 | Logical OR NOT | N,Z,C | 3.5.2 on page 85 |
+| ORR, ORRS | {Rd,} Rn, Op2 | Logical OR | N,Z,C | 3.5.2 on page 85 |
+| PKHTB, PKHBT | {Rd,} Rn, Rm, Op2 | Pack Halfword | — | 3.8.1 on page 135 |
+| POP | reglist | Pop registers from stack | — | 3.4.7 on page 78 |
+| PUSH | reglist | Push registers onto stack | — | 3.4.7 on page 78 |
+| QADD | {Rd,} Rn, Rm | Saturating double and add | — | 3.7.3 on page 128 |
+| QADD16 | {Rd,} Rn, Rm | Saturating add 16 | — | 3.7.3 on page 128 |
+| QADD8 | {Rd,} Rn, Rm | Saturating add 8 | — | 3.7.3 on page 128 |
+| QASX | {Rd,} Rn, Rm | Saturating add and subtract with exchange | — | 3.7.4 on page 129 |
+| QSAX | {Rd,} Rn, Rm | Saturating subtract and add with exchange | — | 3.7.4 on page 129 |
+| QSUB | {Rd,} Rn, Rm | Saturating subtract | — | 3.7.3 on page 128 |
+| QSUB16 | {Rd,} Rn, Rm | Saturating subtract 16 | — | 3.7.3 on page 128 |
+| QSUB8 | {Rd,} Rn, Rm | Saturating subtract 8 | — | 3.7.3 on page 128 |
+| RBIT | Rd, Rm | Reverse bits | — | 3.5.8 on page 92 |
+| REV | Rd, Rm | Reverse byte order in a word | — | 3.5.8 on page 92 |
+| REV16 | Rd, Rm | Reverse byte order in each halfword | — | 3.5.8 on page 92 |
+| REVSH | Rd, Rm | Reverse byte order in bottom halfword and sign extend | — | 3.5.8 on page 92 |
+| ROR, RORS | Rd, Rm, <Rs\|#n> | Rotate right | N,Z,C | 3.5.3 on page 86 |
+| RRX, RRXS | Rd, Rm | Rotate right with extend | N,Z,C | 3.5.3 on page 86 |
+| SADDSUBX | {Rd,} Rn, Rm | Signed add and subtract with exchange | — | 3.7.4 on page 129 |
+| SADD8 | {Rd,} Rn, Rm | Signed add 8 | — | 3.7.4 on page 129 |
+| SADD16 | {Rd,} Rn, Rm | Signed add 16 | — | 3.7.4 on page 129 |
+| SASX | {Rd,} Rn, Rm | Signed add and subtract with exchange | — | 3.7.4 on page 129 |
+| SBC, SBCS | {Rd,} Rn, Op2 | Subtract with carry | N,Z,C,V | 3.5.5 on page 88 |
+| SBFX | Rd, Rn, #lsb, #width | Signed bit field extract | — | 3.9.2 on page 140 |
+| SDIV | {Rd,} Rn, Rm | Signed divide | — | 3.5.9 on page 93 |
+| SEL | {Rd,} Rn, Rm | Select bytes | — | 3.7.4 on page 129 |
+| SEV | — | Send event | — | 3.11.9 on page 189 |
+| SHADD8 | {Rd,} Rn, Rm | Signed halving add 8 | — | 3.7.4 on page 129 |
+| SHADD16 | {Rd,} Rn, Rm | Signed halving add 16 | — | 3.7.4 on page 129 |
+| SHASX | {Rd,} Rn, Rm | Signed halving add and subtract with exchange | — | 3.7.4 on page 129 |
+| SHSAX | {Rd,} Rn, Rm | Signed halving subtract and add with exchange | — | 3.7.4 on page 129 |
+| SHSUB8 | {Rd,} Rn, Rm | Signed halving subtract 8 | — | 3.7.4 on page 129 |
+| SHSUB16 | {Rd,} Rn, Rm | Signed halving subtract 16 | — | 3.7.4 on page 129 |
+| SMLAD | {Rd,} Rn, Rm, Ra | Signed multiply accumulate long (halfwords) | — | 3.6.2 on page 111 |
+| SMLADX | {Rd,} Rn, Rm, Ra | Signed multiply accumulate long (halfwords) | — | 3.6.2 on page 111 |
+| SMLAL | RdLo, RdHi, Rn, Rm | Signed multiply with accumulate (32x32=64) | — | 3.6.1 on page 110 |
+| SMLALBB | RdLo, RdHi, Rn, Rm | Signed multiply accumulate long (16x16=64) | — | 3.6.2 on page 111 |
+| SMLALD | RdLo, RdHi, Rn, Rm | Signed multiply accumulate long (32x32=64) | — | 3.6.2 on page 111 |
+| SMLALDX | RdLo, RdHi, Rn, Rm | Signed multiply accumulate long (32x32=64) | — | 3.6.2 on page 111 |
+| SMLAWB | {Rd,} Rn, Rm, Ra | Signed multiply accumulate long (32x16=48) | — | 3.6.2 on page 111 |
+| SMLAWT | {Rd,} Rn, Rm, Ra | Signed multiply accumulate long (32x16=48) | — | 3.6.2 on page 111 |
+| SMLSD | {Rd,} Rn, Rm, Ra | Signed multiply subtract difference long | — | 3.6.2 on page 111 |
+| SMLSDX | {Rd,} Rn, Rm, Ra | Signed multiply subtract difference long | — | 3.6.2 on page 111 |
+| SMLSLD | RdLo, RdHi, Rn, Rm | Signed multiply subtract long | — | 3.6.2 on page 111 |
+| SMLSLDX | RdLo, RdHi, Rn, Rm | Signed multiply subtract long | — | 3.6.2 on page 111 |
+| SMMLA | {Rd,} Rn, Rm, Ra | Signed most significant word multiply accumulate | — | 3.6.2 on page 111 |
+| SMMLAR | {Rd,} Rn, Rm, Ra | Signed most significant word multiply accumulate | — | 3.6.2 on page 111 |
+| SMMLS | {Rd,} Rn, Rm, Ra | Signed most significant word multiply subtract | — | 3.6.2 on page 111 |
+| SMMLSR | {Rd,} Rn, Rm, Ra | Signed most significant word multiply subtract | — | 3.6.2 on page 111 |
+| SMMUL | {Rd,} Rn, Rm | Signed most significant word multiply | — | 3.6.2 on page 111 |
+| SMMULR | {Rd,} Rn, Rm | Signed most significant word multiply | — | 3.6.2 on page 111 |
+| SMUAD | {Rd,} Rn, Rm | Signed dual multiply add | — | 3.6.2 on page 111 |
+| SMUADX | {Rd,} Rn, Rm | Signed dual multiply add | — | 3.6.2 on page 111 |
+| SMULBB | {Rd,} Rn, Rm | Signed halfword multiply | — | 3.6.2 on page 111 |
+| SMULBT | {Rd,} Rn, Rm | Signed halfword multiply | — | 3.6.2 on page 111 |
+
+**Table 21. Cortex-M4 instructions (continued)**
+
+| Mnemonic | Operands | Brief description | Flags | Page |
+|----------|----------|-------------------|-------|------|
+
+> 原始图片：imgs/page_52_*.png（无图则注明无图）
@@ -0,0 +1,72 @@
+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 197
+
+Core peripherals
+
+```assembly
+; R3 = attributes
+; R4 = address
+LDR R0,=MPU_RNR           ; 0xE000ED98, MPU region number register
+STR R1, [R0, #0x0]        ; Region Number
+BIC R2, R2, #1            ; Disable
+STRH R2, [R0, #0x8]       ; Region Size and Enable
+STR R4, [R0, #0x4]        ; Region Base Address
+STRH R3, [R0, #0xA]       ; Region Attribute
+ORR R2, #1                ; Enable
+STRH R2, [R0, #0x8]       ; Region Size and Enable
+```
+
+Software must use memory barrier instructions:
+•
+Before MPU setup if there might be outstanding memory transfers, such as buffered
+writes, that might be affected by the change in MPU settings
+•
+After MPU setup if it includes memory transfers that must use the new MPU settings.
+However, memory barrier instructions are not required if the MPU setup process starts by
+entering an exception handler, or is followed by an exception return, because the exception
+entry and exception return mechanism cause memory barrier behavior.
+Software does not need any memory barrier instructions during MPU setup, because it
+accesses the MPU through the PPB, which is a Strongly-Ordered memory region.
+For example, if you want all of the memory access behavior to take effect immediately after
+the programming sequence, use a DSB instruction and an ISB instruction:
+•
+A DSB is required after changing MPU settings, such as at the end of context switch.
+•
+An ISB required if the code that programs the MPU region or regions is entered using
+a branch or call. If the programming sequence is entered using a return from exception,
+or by taking an exception, then you do not require an ISB.
+Updating an MPU region using multi-word writes
+You can program directly using multi-word writes, depending on how the information is
+divided. Consider the following reprogramming:
+
+```assembly
+; R1 = region number
+; R2 = address
+; R3 = size, attributes in one
+LDR R0, =MPU_RNR
+; 0xE000ED98, MPU region number register
+STR R1, [R0, #0x0]
+; Region Number
+STR R2, [R0, #0x4]
+; Region Base Address
+STR R3, [R0, #0x8]
+; Region Attribute, Size and Enable
+```
+
+Use an STM instruction to optimize this:
+
+```assembly
+; R1 = region number
+; R2 = address
+; R3 = size, attributes in one
+LDR R0, =MPU_RNR
+; 0xE000ED98, MPU region number register
+STM R0, {R1-R3}
+; Region Number, address, attribute, size and enable
+```
+
+You can do this in two words for pre-packed information. This means that the RBAR
+contains the required region number and had the VALID bit set to 1, see MPU region base
+address register (MPU_RBAR) on page 203. Use this when the data is statically packed, for
+example in a boot loader:
+
+> 原始图片：imgs/page_197_*.png（无图则注明无图）
@@ -0,0 +1,150 @@
+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 237
+
+4.4.10
+Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)
+
+Address offset: 0x28
+Reset value: 0x0000 0000
+Required privilege: Privileged
+
+The following subsections describe the subregisters that make up the CFSR:
+•
+Usage fault status register (UFSR) on page 238
+•
+Bus fault status register (BFSR) on page 239
+•
+Memory management fault address register (MMFSR) on page 240
+
+The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
+•
+Access the complete CFSR with a word access to 0xE000ED28
+•
+Access the MMFSR with a byte access to 0xE000ED28
+•
+Access the MMFSR and BFSR with a halfword access to 0xE000ED28
+•
+Access the BFSR with a byte access to 0xE000ED29
+•
+Access the UFSR with a halfword access to 0xE000ED2A.
+
+The CFSR indicates the cause of a memory management fault, bus fault, or usage fault.
+
+**Figure 20. CFSR subregisters**
+
+![图 20](imgs/page_237_fig_20.png)
+
+Memory Management
+Fault Status Register
+31
+16 15
+8
+7
+0
+Usage Fault Status Register
+Bus Fault Status
+Register
+UFSR
+BFSR
+MMFSR
+31
+30
+29
+28
+27
+26
+25
+24
+23
+22
+21
+20
+19
+18
+17
+16
+Reserved
+DIVBY
+ZERO
+UNALI
+GNED
+Reserved
+NOCP
+INVPC
+INV
+STATE
+UNDEF
+INSTR
+rc_w1
+rc_w1
+rc_w1
+rc_w1
+rc_w1
+rc_w1
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
+BFARV
+ALID
+Reserv
+ed
+LSP
+ERR
+STK
+ERR
+UNSTK
+ERR
+IMPRE
+CIS
+ERR
+PRECI
+S ERR
+IBUS
+ERR
+MMAR
+VALID
+Reserv
+ed
+MLSP
+ERR
+MSTK
+ERR
+M
+UNSTK
+ERR
+Res.
+DACC
+VIOL
+IACC
+VIOL
+rw
+rw
+rw
+rw
+rw
+rw
+rw
+rw
+rw
+rw
+rw
+rw
+rw
+
+Bits 31:16 UFSR: see Usage fault status register (UFSR) on page 238
+Bits 15:8 BFSR: see Bus fault status register (BFSR) on page 239
+Bits 7:0 MMFSR: see Memory management fault address register (MMFSR) on page 240
+
+> 原始图片：imgs/page_237_fig_20.png
@@ -0,0 +1,43 @@
+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 238
+
+4.4.11
+Usage fault status register (UFSR)
+
+Bits 31:26 Reserved, must be kept cleared
+Bit 25 DIVBYZERO: Divide by zero usage fault. When the processor sets this bit to 1, the PC value
+stacked for the exception return points to the instruction that performed the divide by zero.
+Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see
+Configuration and control register (CCR) on page 231.
+0: No divide by zero fault, or divide by zero trapping not enabled
+1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
+Bit 24 UNALIGNED: Unaligned access usage fault. Enable trapping of unaligned accesses by
+setting the UNALIGN_TRP bit in the CCR to 1, see Configuration and control register (CCR)
+on page 231.
+Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
+UNALIGN_TRP.
+0: No unaligned access fault, or unaligned access trapping not enabled
+1: the processor has made an unaligned memory access.
+Bits 23:20 Reserved, must be kept cleared
+Bit 19 NOCP: No coprocessor usage fault. The processor does not support coprocessor instructions:
+0: No usage fault caused by attempting to access a coprocessor
+1: the processor has attempted to access a coprocessor.
+Bit 18 INVPC: Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:
+When this bit is set to 1, the PC value stacked for the exception return points to the instruction
+that tried to perform the illegal load of the PC.
+0: No invalid PC load usage fault
+1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an
+invalid context, or an invalid EXC_RETURN value.
+Bit 17 INVSTATE: Invalid state usage fault. When this bit is set to 1, the PC value stacked for
+the exception return points to the instruction that attempted the illegal use of the EPSR.
+This bit is not set to 1 if an undefined instruction uses the EPSR.
+0: No invalid state usage fault
+1: The processor has attempted to execute an instruction that makes illegal use of the
+EPSR.
+Bit 16 UNDEFINSTR: Undefined instruction usage fault. When this bit is set to 1, the PC value
+stacked for the exception return points to the undefined instruction.
+An undefined instruction is an instruction that the processor cannot decode.
+0: No undefined instruction usage fault
+1: The processor has attempted to execute an undefined instruction.
+Bits 15:0 Reserved, must be kept cleared
+
+> 原始图片：imgs/page_238_*.png（无图则注明无图）
@@ -0,0 +1,61 @@
+# PDF 转 Markdown 输出说明
+
+**文档**：STM32 Cortex®-M4 MCUs and MPUs Programming Manual (PM0214 Rev 10)
+
+## 处理概述
+
+本目录包含从 PDF 第 1-262 页中提取的 12 页原始文本，经 v5 提示词规则转换后的 Markdown 文件。
+
+## 提示词来源
+
+- 提示词文件：`/tmp/pdf-test/llm-pdf-to-md-prompt.md`
+- 来源：本地仓库 `~/.hermes/knowledge/llm-pdf-to-md-prompt.md`
+
+## 输出文件清单
+
+| 文件名 | 对应页码 | 内容说明 |
+|--------|----------|----------|
+| `00_目录.md` | p2 | 目录页 |
+| `1_About_this_document_p12.md` | p12 | 第1章 About this document |
+| `1.3_About_the_STM32_Cortex-M4_processor_and_core_peripherals_p13.md` | p13 | 1.3节（含Figure 1框图） |
+| `2.1.3_Core_registers_p18.md` | p18 | 2.1.3节 Core registers（含Figure 2 + Table 2, Table 3） |
+| `2.1.4_Exceptions_and_interrupts_p20.md` | p20 | PSR寄存器（含Figure 3, Figure 4 + Table 4） |
+| `2.1.4_Exceptions_and_interrupts_p21.md` | p21 | APSR寄存器描述（Table 5） |
+| `3.5_Instruction_summary_p51.md` | p51 | Cortex-M4指令表（前半部分，Table 21） |
+| `3.5_Instruction_summary_p52.md` | p52 | Cortex-M4指令表（后半部分，Table 21 continued） |
+| `4.3_Memory_Protection_Unit_p197.md` | p197 | MPU代码示例 |
+| `4.4.10_Configurable_fault_status_register_p237.md` | p237 | CFSR寄存器描述（含Figure 20） |
+| `4.4.11_Usage_fault_status_register_p238.md` | p238 | UFSR寄存器位描述 |
+
+## 封面页处理
+
+- 封面页（p1）：`/tmp/pdf-test/pages/page_1.txt` 已有原始文本
+- 封面页不生成正文 MD 文件，截图存档用 `imgs/page_1_cover.png`
+
+## 原始文本来源
+
+原始文本目录：`/tmp/pdf-test/pages/`
+
+```
+page_1.txt   - 封面
+page_2.txt   - 目录
+page_12.txt  - About this document
+page_13.txt  - About the STM32 Cortex-M4 processor
+page_18.txt  - Core registers (新增)
+page_20.txt  - PSR registers (新增)
+page_21.txt  - APSR register (新增)
+page_51.txt  - Instruction summary
+page_52.txt  - Instruction summary (continued)
+page_197.txt - MPU code example (新增)
+page_237.txt - CFSR register (新增)
+page_238.txt - UFSR register (新增)
+```
+
+## 处理规则（v5提示词）
+
+1. **目录**：单独生成 `00_目录.md`，三列格式（章节号|标题|页码）
+2. **文件名**：按 `章节号_标题_p{页码}.md` 规则命名
+3. **表格**：严格还原原始结构，表头和标题行独立处理
+4. **图片**：使用 `![图 X](imgs/page_{页码}_fig_{编号}.png)` 占位符
+5. **寄存器缩写**：保留原文（r、rw、rc_w0 等）
+6. **代码块**：汇编代码用 ` ```assembly ` 包裹