test: PDF洗MD v5 第二批测试 — 12页（含寄存器/代码/位域表）

新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
2026-06-10 16:03:04 +08:00
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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 197
+
+Core peripherals
+
+```assembly
+; R3 = attributes
+; R4 = address
+LDR R0,=MPU_RNR           ; 0xE000ED98, MPU region number register
+STR R1, [R0, #0x0]        ; Region Number
+BIC R2, R2, #1            ; Disable
+STRH R2, [R0, #0x8]       ; Region Size and Enable
+STR R4, [R0, #0x4]        ; Region Base Address
+STRH R3, [R0, #0xA]       ; Region Attribute
+ORR R2, #1                ; Enable
+STRH R2, [R0, #0x8]       ; Region Size and Enable
+```
+
+Software must use memory barrier instructions:
+•
+Before MPU setup if there might be outstanding memory transfers, such as buffered
+writes, that might be affected by the change in MPU settings
+•
+After MPU setup if it includes memory transfers that must use the new MPU settings.
+However, memory barrier instructions are not required if the MPU setup process starts by
+entering an exception handler, or is followed by an exception return, because the exception
+entry and exception return mechanism cause memory barrier behavior.
+Software does not need any memory barrier instructions during MPU setup, because it
+accesses the MPU through the PPB, which is a Strongly-Ordered memory region.
+For example, if you want all of the memory access behavior to take effect immediately after
+the programming sequence, use a DSB instruction and an ISB instruction:
+•
+A DSB is required after changing MPU settings, such as at the end of context switch.
+•
+An ISB required if the code that programs the MPU region or regions is entered using
+a branch or call. If the programming sequence is entered using a return from exception,
+or by taking an exception, then you do not require an ISB.
+Updating an MPU region using multi-word writes
+You can program directly using multi-word writes, depending on how the information is
+divided. Consider the following reprogramming:
+
+```assembly
+; R1 = region number
+; R2 = address
+; R3 = size, attributes in one
+LDR R0, =MPU_RNR
+; 0xE000ED98, MPU region number register
+STR R1, [R0, #0x0]
+; Region Number
+STR R2, [R0, #0x4]
+; Region Base Address
+STR R3, [R0, #0x8]
+; Region Attribute, Size and Enable
+```
+
+Use an STM instruction to optimize this:
+
+```assembly
+; R1 = region number
+; R2 = address
+; R3 = size, attributes in one
+LDR R0, =MPU_RNR
+; 0xE000ED98, MPU region number register
+STM R0, {R1-R3}
+; Region Number, address, attribute, size and enable
+```
+
+You can do this in two words for pre-packed information. This means that the RBAR
+contains the required region number and had the VALID bit set to 1, see MPU region base
+address register (MPU_RBAR) on page 203. Use this when the data is statically packed, for
+example in a boot loader:
+
+> 原始图片：imgs/page_197_*.png（无图则注明无图）