test: PDF洗MD v5 第二批测试 — 12页（含寄存器/代码/位域表）

新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述)
原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表

Co-Authored-By: Claude <noreply@anthropic.com>

source/page_20.txt

@@ -0,0 +1,80 @@
+The Cortex-M4 processor
+PM0214
+20/262
+PM0214 Rev 10
+These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is 
+shown in Figure 3 and Figure 4.
+Figure 3. APSR, IPSR and EPSR bit assignment
+Figure 4. PSR bit assignment 
+Access these registers individually or as a combination of any two or all three registers, 
+using the register name as an argument to the MSR or MRS instructions. For example:
+•
+Read all of the registers using PSR with the MRS instruction.
+•
+Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.
+The PSR combinations and attributes are:
+          
+See the instruction descriptions MRS on page 186 and MSR on page 187 for more 
+information about how to access the program status registers.
+Table 4. PSR register combinations 
+Register
+Type
+Combination
+PSR
+read-write(1), (2)
+1.
+The processor ignores writes to the IPSR bits.
+2.
+Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
+APSR, EPSR, and IPSR
+IEPSR
+read-only
+EPSR and IPSR
+IAPSR
+read-write(1)
+APSR and IPSR
+EAPSR
+read-write(2)
+APSR and EPSR
+25 24 23
+Reserved
+ISR_NUMBER
+31 30 29 28 27
+N Z C V
+0
+Reserved
+APSR
+IPSR
+EPSR
+Reserved
+Reserved
+26
+16 15
+10 9
+Reserved
+ICI/IT
+ICI/IT
+T
+Q
+8
+19
+20
+GE[3:0]
+Reserved
+25 24 23
+31 30 29 28 27
+N Z C V
+0
+PSR
+Reserved
+26
+16 15
+10 9
+ICI/IT
+Q
+8
+19
+20
+GE[3:0]
+Reserved
+ISR_NUMBER