test: PDF洗MD v3 — 截图增强版(12页测试)
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来源:PM0214 Rev 10,Page 13
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# 1.3 About the STM32 Cortex-M4 processor and core peripherals
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The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:
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- Outstanding processing performance combined with fast interrupt handling
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- Enhanced system debug with extensive breakpoint and trace capabilities
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- Efficient processor core, system and memories
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- Ultra-low power consumption with integrated sleep modes
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- Platform security robustness, with integrated memory protection unit (MPU)
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The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including:
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- IEEE754-compliant single-precision floating-point computation
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- A range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities
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- Saturating arithmetic
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- Dedicated hardware division
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## Figure 1. STM32 Cortex-M4 implementation
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> 架构框图展示了 Cortex-M4 处理器的内部结构,包含以下主要组件:
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| 组件 | 说明 |
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|------|------|
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| Cortex-M4 processor | 处理器核心 |
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| FPU | 浮点运算单元 |
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| NVIC | 嵌套向量中断控制器 |
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| Memory protection unit | 内存保护单元 |
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| Debug access port | 调试访问端口 |
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| Embedded Trace Macrocell | 嵌入式跟踪宏单元 |
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| Serial wire viewer | 串行线查看器 |
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| Bus matrix | 总线矩阵 |
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| Flash patch | Flash补丁 |
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| Data watchpoints | 数据监视点 |
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| Code interface | 代码接口 |
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| SRAM and peripheral interface | SRAM和外设接口 |
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## 寄存器位访问类型
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| 缩写 | 含义 |
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|------|------|
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| read/clear (rc_w1) | Software can read as well as clear this bit by writing 1. Writing '0' has no effect on the bit value. |
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| read/clear (rc_w0) | Software can read as well as clear this bit by writing 0. Writing '1' has no effect on the bit value. |
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| toggle (t) | Software can only toggle this bit by writing '1'. Writing '0' has no effect. |
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| Reserved (Res.) | Reserved bit, must be kept at reset value. |
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> 原始图片:imgs/page_13.png(无图则注明无图)
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