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来源：PM0214 Rev 10，Page 2
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| 章节号 | 标题 | 页码 |
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|--------|------|------|
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| 1 | About this document | 12 |
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| 1.1 | Typographical conventions | 12 |
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| 1.2 | List of abbreviations for registers | 12 |
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| 1.3 | About the STM32 Cortex-M4 processor and core peripherals | 13 |
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| 1.3.1 | System level interface | 14 |
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| 1.3.2 | Integrated configurable debug | 14 |
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| 1.3.3 | Cortex-M4 processor features and benefits summary | 15 |
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| 1.3.4 | Cortex-M4 core peripherals | 16 |
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| 2 | The Cortex-M4 processor | 17 |
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| 2.1 | Programmers model | 17 |
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| 2.1.1 | Processor mode and privilege levels for software execution | 17 |
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| 2.1.2 | Stacks | 17 |
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| 2.1.3 | Core registers | 18 |
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| 2.1.4 | Exceptions and interrupts | 26 |
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| 2.1.5 | Data types | 26 |
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| 2.1.6 | The Cortex microcontroller software interface standard (CMSIS) | 26 |
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| 2.2 | Memory model | 28 |
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| 2.2.1 | Memory regions, types and attributes | 29 |
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| 2.2.2 | Memory system ordering of memory accesses | 29 |
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| 2.2.3 | Behavior of memory accesses | 30 |
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| 2.2.4 | Software ordering of memory accesses | 31 |
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| 2.2.5 | Bit-banding | 32 |
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| 2.2.6 | Memory endianness | 34 |
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| 2.2.7 | Synchronization primitives | 34 |
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| 2.2.8 | Programming hints for the synchronization primitives | 36 |
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| 2.3 | Exception model | 37 |
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| 2.3.1 | Exception states | 37 |
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| 2.3.2 | Exception types | 37 |
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| 2.3.3 | Exception handlers | 39 |
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| 2.3.4 | Vector table | 40 |
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| 2.3.5 | Exception priorities | 41 |
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| 2.3.6 | Interrupt priority grouping | 41 |
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| 2.3.7 | Exception entry and return | 42 |
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> 原始图片：imgs/page_2.png（无图则注明无图）
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来源：PM0214 Rev 10，Page 13
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# 1.3 About the STM32 Cortex-M4 processor and core peripherals
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The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:
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- Outstanding processing performance combined with fast interrupt handling
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- Enhanced system debug with extensive breakpoint and trace capabilities
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- Efficient processor core, system and memories
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- Ultra-low power consumption with integrated sleep modes
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- Platform security robustness, with integrated memory protection unit (MPU)
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The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including:
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- IEEE754-compliant single-precision floating-point computation
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- A range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities
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- Saturating arithmetic
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- Dedicated hardware division
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## Figure 1. STM32 Cortex-M4 implementation
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> 架构框图展示了 Cortex-M4 处理器的内部结构，包含以下主要组件：
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| 组件 | 说明 |
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|------|------|
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| Cortex-M4 processor | 处理器核心 |
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| FPU | 浮点运算单元 |
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| NVIC | 嵌套向量中断控制器 |
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| Memory protection unit | 内存保护单元 |
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| Debug access port | 调试访问端口 |
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| Embedded Trace Macrocell | 嵌入式跟踪宏单元 |
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| Serial wire viewer | 串行线查看器 |
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| Bus matrix | 总线矩阵 |
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| Flash patch | Flash补丁 |
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| Data watchpoints | 数据监视点 |
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| Code interface | 代码接口 |
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| SRAM and peripheral interface | SRAM和外设接口 |
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## 寄存器位访问类型
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| 缩写 | 含义 |
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|------|------|
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| read/clear (rc_w1) | Software can read as well as clear this bit by writing 1. Writing '0' has no effect on the bit value. |
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| read/clear (rc_w0) | Software can read as well as clear this bit by writing 0. Writing '1' has no effect on the bit value. |
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| toggle (t) | Software can only toggle this bit by writing '1'. Writing '0' has no effect. |
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| Reserved (Res.) | Reserved bit, must be kept at reset value. |
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> 原始图片：imgs/page_13.png（无图则注明无图）
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来源：PM0214 Rev 10，Page 12
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# About this document
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This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation.
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This material is for microcontroller software and hardware engineers, including those who have no experience of Arm products.
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This document applies to Arm®(a)-based devices.
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## 1.1 Typographical conventions
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The typographical conventions used in this document are:
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## 1.2 List of abbreviations for registers
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The following abbreviations are used in register descriptions:
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| Abbreviation | Meaning |
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|--------------|---------|
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| read/write (rw) | Software can read and write to these bits. |
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| read-only (r) | Software can only read these bits. |
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| write-only (w) | Software can only write to this bit. Reading the bit returns the reset value. |
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**Typographical conventions:**
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| Style | Meaning |
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|-------|---------|
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| *italic* | Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. |
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| `<` and `>` | Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: `LDRSB<cond> <Rt>, [<Rn>, #<offset>]` |
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| **bold** | Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. |
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| `monospace` | Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. |
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| `monospace` (underlined) | Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. |
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| *monospace italic* | Denotes arguments to monospace text where the argument is to be replaced by a specific value. |
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| **`monospace bold`** | Denotes language keywords when used outside example code. |
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> Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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> 原始图片：imgs/page_12.png（无图则注明无图）
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# 2.1.3 Core registers
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## Figure 2. Processor core registers
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> 原始图片：imgs/page_18_fig_2.png
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**寄存器示意图**（Figure 2）：
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- 顶部显示 **PSR**（Program Status Register，含 APSR、EPSR、IPSR 三个子寄存器）
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- 中部显示 **PRIMASK**、**FAULTMASK**、**BASEPRI**、**CONTROL** 等特殊寄存器
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- 底部显示 **SP**（含 MSP 和 PSP）、**LR**、**PC** 以及 **R0-R12** 通用寄存器
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---
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## Table 2. Summary of processor mode, execution privilege level, and stack usage
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| Processor mode | Used to execute | Privilege level for software execution | Stack used |
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|----------------|-----------------|---------------------------------------|------------|
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| Thread | Applications | Privileged or unprivileged (1) | Main stack or process stack (1) |
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| Handler | Exception handlers | Always privileged | Main stack |
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> 1. See CONTROL register on page 25.
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---
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## Table 3. Core register set summary
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| Name | Type (1) | Required privilege (2) | Reset value | Description |
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|------|----------|------------------------|-------------|-------------|
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| R0-R12 | read-write | Either | Unknown | General-purpose registers on page 19 |
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| MSP | read-write | Privileged | See description | Stack pointer on page 19 |
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| PSP | read-write | Either | Unknown | Stack pointer on page 19 |
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| LR | read-write | Either | 0xFFFFFFFF | Link register on page 19 |
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| PC | read-write | Either | See description | Program counter on page 19 |
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> 1. Type 列中的 "read-write" 表示该寄存器可被程序读写访问。
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> 2. Required privilege 列表示操作该寄存器所需的权限级别："Privileged" 仅允许特权模式，"Either" 表示特权模式和用户模式均可操作。
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---
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**说明**：本页面包含 3 个核心内容元素：
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1. **Figure 2** — 处理器核心寄存器示意图，展示各寄存器的层次结构与从属关系
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2. **Table 2** — 处理器模式、执行特权级、栈使用情况的概览表
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3. **Table 3** — 核心寄存器集的功能与属性汇总表
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来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 18
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来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 20
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These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is
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shown in Figure 3 and Figure 4.
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**Figure 3. APSR, IPSR and EPSR bit assignment**
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**Figure 4. PSR bit assignment**
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Access these registers individually or as a combination of any two or all three registers,
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using the register name as an argument to the MSR or MRS instructions. For example:
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- Read all of the registers using PSR with the MRS instruction.
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- Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.
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The PSR combinations and attributes are:
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See the instruction descriptions MRS on page 186 and MSR on page 187 for more
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information about how to access the program status registers.
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**Table 4. PSR register combinations**
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| Register | Type | Combination |
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|----------|------|-------------|
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| PSR | read-write(1), (2) | APSR, EPSR, and IPSR |
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| IEPSR | read-only | EPSR and IPSR |
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| IAPSR | read-write(1) | APSR and IPSR |
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| EAPSR | read-write(2) | APSR and EPSR |
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1. The processor ignores writes to the IPSR bits.
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2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
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|25 24 23 | Reserved | ISR_NUMBER | 31 30 29 28 27 | N Z C V | 0 | Reserved |
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|----------|----------|------------|----------------|---------|---|----------|
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| 26 | Reserved | | 16 15 | ICI/IT | ICI/IT | T | Q |
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| 8 | 19 | 20 | GE[3:0] | Reserved | | |
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> 原始图片：imgs/page_20_fig_3.png, imgs/page_20_fig_4.png
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# 2.1.6 Usage Fault Status Register (UFSR)
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> **寄存器名称**：Usage Fault Status Register
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> **偏移地址**：UFSR（位于 SCB 内）
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> **访问权限**：读/写（软件可写入 1 清除对应位）
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> **初始复位值**：0x0000\_0000
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> **说明**：UFSR 指示发生了何种 Usage Fault 错误。写 1 到对应位可清除该位。
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---
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## 位域定义
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| 位号 | 位域名称 | 类型 | 复位值 | 描述 |
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|:----:|:--------:|:----:|:------:|:------|
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| 31:26 | Reserved | — | 0 | 保留位，必须保持清零 |
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| 25 | DIVBYZERO | RW | 0 | **Divide by zero usage fault**。当该位被置 1 时，堆栈保存的 PC 值指向执行了 SDIV 或 UDIV 指令且除数为 0 的那条指令。需通过 CCR 的 DIV\_0\_TRP 位使能除零错误捕获。0 = 无除零错误，或未使能捕获；1 = 处理器执行了除数为 0 的 SDIV/UDIV 指令 |
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| 24 | UNALIGNED | RW | 0 | **Unaligned access usage fault**。通过 CCR 的 UNALIGN\_TRP 位使能未对齐访问捕获。注意：未对齐的 LDM、STM、LDRD、STRD 指令无论 UNALIGN\_TRP 设置如何均会触发错误。0 = 无未对齐访问错误，或未使能捕获；1 = 处理器执行了未对齐内存访问 |
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| 23:20 | Reserved | — | 0 | 保留位，必须保持清零 |
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| 19 | NOCP | RW | 0 | **No coprocessor usage fault**。处理器不支持协处理器指令。0 = 未因访问协处理器而触发 usage fault；1 = 处理器尝试访问了协处理器 |
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| 18 | INVPC | RW | 0 | **Invalid PC load usage fault**（由无效的 EXC\_RETURN 加载 PC 导致）。当该位置 1 时，堆栈保存的 PC 值指向那条试图非法加载 PC 的指令。0 = 无无效 PC 加载错误；1 = 处理器尝试将非法 EXC\_RETURN 加载到 PC（因无效上下文或无效 EXC\_RETURN 值） |
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| 17 | INVSTATE | RW | 0 | **Invalid state usage fault**。当该位置 1 时，堆栈保存的 PC 值指向那条非法使用 EPSR 的指令。若某未定义指令使用了 EPSR，不会置 1。0 = 无无效状态错误；1 = 处理器尝试执行了非法使用 EPSR 的指令 |
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| 16 | UNDEFINSTR | RW | 0 | **Undefined instruction usage fault**。当该位置 1 时，堆栈保存的 PC 值指向该未定义指令。未定义指令是指处理器无法解码的指令。0 = 无未定义指令错误；1 = 处理器尝试执行了未定义指令 |
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---
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## 字段值摘要
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| 位域 | = 0 | = 1 |
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|:-----|:----|:----|
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| **DIVBYZERO** | 无除零 fault，或未使能捕获 | 执行了除数为 0 的 SDIV/UDIV |
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| **UNALIGNED** | 无未对齐 fault，或未使能捕获 | 执行了未对齐内存访问 |
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| **NOCP** | 未因访问协处理器触发 fault | 尝试访问了协处理器 |
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| **INVPC** | 无无效 PC 加载 fault | 尝试非法加载 EXC\_RETURN 到 PC |
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| **INVSTATE** | 无无效状态 fault | 尝试执行了 EPSR 非法使用 |
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| **UNDEFINSTR** | 无未定义指令 fault | 尝试执行了未定义指令 |
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---
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## 异常返回与 PC 堆栈值
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当 UFSR 中任意位被置 1 时，异常返回时堆栈保存的 PC 值指向**触发该 fault 的那条指令**（用于调试定位）。
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|
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---
|
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## 相关寄存器
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|
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- **CCR** (Configuration and Control Register)：控制 DIV\_0\_TRP 和 UNALIGN\_TRP 位的使能（第 231 页）
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- **HFSR** (HardFault Status Register)：HardFault 状态寄存器
|
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- **MMFAR** (MemManage Fault Address Register)：MemManage 错误地址寄存器
|
||||
|
||||
---
|
||||
|
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## 设计说明
|
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|
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- UFSR 为**粘滞 sticky** 设计：写入 1 清除对应位，写入 0 保持不变
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- 所有 Reserved 位写入 1 会产生不可预测行为
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- 复位后所有位清零，表示无 Usage Fault
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@@ -0,0 +1,20 @@
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来源：PM0214 Rev 10，Page 21
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## Application program status register
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|
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The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 3 on page 18 for its attributes. The bit assignment is:
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|
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**Table 5. APSR bit definitions**
|
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|
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| Bits | Description |
|
||||
|------|-------------|
|
||||
| Bit 31 | N: Negative or less than flag: 0: Operation result was positive, zero, greater than, or equal; 1: Operation result was negative or less than. |
|
||||
| Bit 30 | Z: Zero flag: 0: Operation result was not zero; 1: Operation result was zero. |
|
||||
| Bit 29 | C: Carry or borrow flag: 0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit; 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit. |
|
||||
| Bit 28 | V: Overflow flag: 0: Operation did not result in an overflow; 1: Operation resulted in an overflow. |
|
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| Bit 27 | Q: DSP overflow and saturation flag: Sticky saturation flag. 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero; 1: Indicates when an SSAT or USAT instruction results in saturation, or indicates a DSP overflow. This bit is cleared to zero by software using an MRS instruction. |
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| Bits 26:20 | Reserved. |
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| Bits 19:16 | GE[3:0]: Greater than or Equal flags. See SEL on page 105 for more information. |
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| Bits 15:0 | Reserved. |
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> 原始图片：imgs/page_21_cover.png（无图则注明无图）
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@@ -0,0 +1,38 @@
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来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 51
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|
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The STM32 Cortex-M4 instruction set
|
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|
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**Table 21. Cortex-M4 instructions (continued)**
|
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|
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| Mnemonic | Operands | Brief description | Flags | Page |
|
||||
|----------|----------|-------------------|-------|------|
|
||||
| AND, ANDS | {Rd,} Rn, Op2 | Logical AND | N,Z,C | 3.5.2 on page 85 |
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||||
| ASR, ASRS | Rd, Rm, <Rs|#n> | Arithmetic shift right | N,Z,C | 3.5.3 on page 86 |
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| B | label | Branch | — | 3.9.5 on page 142 |
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||||
| BFC | Rd, #lsb, #width | Bit field clear | — | 3.9.1 on page 139 |
|
||||
| BFI | Rd, Rn, #lsb, #width | Bit field insert | — | 3.9.1 on page 139 |
|
||||
| BIC, BICS | {Rd,} Rn, Op2 | Bit clear | N,Z,C | 3.5.2 on page 85 |
|
||||
| BKPT | #imm | Breakpoint | — | 3.11.1 on page 181 |
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||||
| BL | label | Branch with link | — | 3.9.5 on page 142 |
|
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| BLX | Rm | Branch indirect with link | — | 3.9.5 on page 142 |
|
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| BX | Rm | Branch indirect | — | 3.9.5 on page 142 |
|
||||
| CBNZ | Rn, label | Compare and branch if non zero | — | 3.9.6 on page 144 |
|
||||
| CBZ | Rn, label | Compare and branch if zero | — | 3.9.6 on page 144 |
|
||||
| CLREX | — | Clear exclusive | — | 3.4.9 on page 80 |
|
||||
| CLZ | Rd, Rm | Count leading zeros | — | 3.5.4 on page 87 |
|
||||
| CMN | Rn, Op2 | Compare negative | N,Z,C,V | 3.5.5 on page 88 |
|
||||
| CMP | Rn, Op2 | Compare | N,Z,C,V | 3.5.5 on page 88 |
|
||||
| CPSID | iflags | Change processor state, disable interrupts | — | 3.11.2 on page 182 |
|
||||
| CPSIE | iflags | Change processor state, enable interrupts | — | 3.11.2 on page 182 |
|
||||
| DMB | — | Data memory barrier | — | 3.11.4 on page 184 |
|
||||
| DSB | — | Data synchronization barrier | — | 3.11.4 on page 184 |
|
||||
| EOR, EORS | {Rd,} Rn, Op2 | Exclusive OR | N,Z,C | 3.5.2 on page 85 |
|
||||
| ISB | — | Instruction synchronization barrier | — | 3.11.5 on page 185 |
|
||||
| IT | — | If-then condition block | — | 3.9.7 on page 145 |
|
||||
| LDM | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
|
||||
| LDMDB, LDMEA | Rn{!}, reglist | Load multiple registers, decrement before | — | 3.4.6 on page 76 |
|
||||
| LDMFD, LDMIA | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
|
||||
| LDR | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
|
||||
| LDRB, LDRBT | Rt, [Rn, #offset] | Load register with byte | — | 3.4 on page 69 |
|
||||
| LDRD | Rt, Rt2, [Rn, #offset] | Load register with two bytes | — | 3.4.2 on page 71 |
|
||||
| LDREX | Rt, [Rn, #offset] | Load register exclusive | — | 3.4.8 on page 79 |
|
||||
@@ -0,0 +1,37 @@
|
||||
来源：PM0214 Rev 10，Page 52
|
||||
|
||||
# Table 21. Cortex-M4 Instructions (continued)
|
||||
|
||||
> 指令汇总表，续前页。
|
||||
|
||||
| Mnemonic | Operands | Brief description | Flags | Page |
|
||||
|----------|----------|-------------------|-------|------|
|
||||
| LDREXB | Rt, [Rn] | Load register exclusive with byte | — | 3.4.8 on page 79 |
|
||||
| LDREXH | Rt, [Rn] | Load register exclusive with halfword | — | 3.4.8 on page 79 |
|
||||
| LDRH, LDRHT | Rt, [Rn, #offset] | Load register with halfword | — | 3.4 on page 69 |
|
||||
| LDRSB, LDRSBT | Rt, [Rn, #offset] | Load register with signed byte | — | 3.4 on page 69 |
|
||||
| LDRSH, LDRSHT | Rt, [Rn, #offset] | Load register with signed halfword | — | 3.4 on page 69 |
|
||||
| LDRT | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
|
||||
| LSL, LSLS | Rd, Rm, <Rs\|#n> | Logical shift left | N,Z,C | 3.5.3 on page 86 |
|
||||
| LSR, LSRS | Rd, Rm, <Rs\|#n> | Logical shift right | N,Z,C | 3.5.3 on page 86 |
|
||||
| MLA | Rd, Rn, Rm, Ra | Multiply with accumulate, 32-bit result | — | 3.6.1 on page 110 |
|
||||
| MLS | Rd, Rn, Rm, Ra | Multiply and subtract, 32-bit result | — | 3.6.1 on page 110 |
|
||||
| MOV, MOVS | Rd, Op2 | Move | N,Z,C | 3.5.6 on page 89 |
|
||||
| MOVT | Rd, #imm16 | Move top | — | 3.5.7 on page 91 |
|
||||
| MOVW, MOV | Rd, #imm16 | Move 16-bit constant | N,Z,C | 3.5.6 on page 89 |
|
||||
| MRS | Rd, spec_reg | Move from special register to general register | — | 3.11.6 on page 186 |
|
||||
| MSR | spec_reg, Rm | Move from general register to special register | N,Z,C,V | 3.11.7 on page 187 |
|
||||
| MUL, MULS | {Rd,} Rn, Rm | Multiply, 32-bit result | N,Z | 3.6.1 on page 110 |
|
||||
| MVN, MVNS | Rd, Op2 | Move NOT | N,Z,C | 3.5.6 on page 89 |
|
||||
| NOP | — | No operation | — | 3.11.8 on page 188 |
|
||||
| ORN, ORNS | {Rd,} Rn, Op2 | Logical OR NOT | N,Z,C | 3.5.2 on page 85 |
|
||||
| ORR, ORRS | {Rd,} Rn, Op2 | Logical OR | N,Z,C | 3.5.2 on page 85 |
|
||||
| PKHTB, PKHBT | {Rd,} Rn, Rm, Op2 | Pack Halfword | — | 3.8.1 on page 135 |
|
||||
| POP | reglist | Pop registers from stack | — | 3.4.7 on page 78 |
|
||||
| PUSH | reglist | Push registers onto stack | — | 3.4.7 on page 78 |
|
||||
| QADD | {Rd,} Rn, Rm | Saturating double and add | — | 3.7.3 on page 128 |
|
||||
| QADD16 | {Rd,} Rn, Rm | Saturating add 16 | — | 3.7.3 on page 128 |
|
||||
| QADD8 | {Rd,} Rn, Rm | Saturating add 8 | — | 3.7.3 on page 128 |
|
||||
| QASX | {Rd,} Rn, Rm | Saturating add and subtract with exchange | — | 3.7.4 on page 129 |
|
||||
|
||||
> 原始截图：imgs/page_52.png（无图则注明无图）
|
||||
@@ -0,0 +1,37 @@
|
||||
# PDF 洗 MD v3 测试结果（截图增强版）
|
||||
|
||||
**文档：** PM0214 Rev 10 - STM32 Cortex-M4 MCUs and MPUs programming manual
|
||||
**测试批次：** 12 页，覆盖封面、目录、正文、表格、代码、位域寄存器等多种页面类型
|
||||
**生成时间：** 2026-06-10
|
||||
|
||||
---
|
||||
|
||||
## 页面清单
|
||||
|
||||
| 页码 | 类型 | 输出文件 |
|
||||
|------|------|---------|
|
||||
| 1 | 封面 | page_1_cover.png（截图） |
|
||||
| 2 | 目录 | 00_目录.md |
|
||||
| 12 | About this document | 1_About_this_document_p12.md |
|
||||
| 13 | 1.3 Cortex-M4 processor | 1.3_Cortex-M4_processor_p13.md |
|
||||
| 18 | 2.1.3 Core registers + Figure 2 | 2.1.3_Core_registers_p18.md |
|
||||
| 20 | 2.1.4 Exceptions & Interrupts（双图） | 2.1.4_Exceptions_and_interrupts_p20.md |
|
||||
| 21 | 2.1 APSR bitfield | 2.1_Application_program_status_register_p21.md |
|
||||
| 51 | 3.5 Instruction summary | 3.5_Instruction_summary_p51.md |
|
||||
| 52 | 3.5 Instruction summary（续） | 3_Table21_Cortex-M4_instructions_p52.md |
|
||||
| 197 | 4.3 MPU assembly code | page_197.md |
|
||||
| 237 | 4.4.10 CFSR bitfield | page_237_cfsr.md |
|
||||
| 238 | 4.4.11 UFSR bitfield | 2.1.6_UFSR_Usage_Fault_Status_Register_p238.md |
|
||||
|
||||
---
|
||||
|
||||
## 主要变化（v3 vs v2）
|
||||
|
||||
- **截图参与决策**：每页同时输入文本 + 截图路径，模型可参照截图修正表格列裂、判断图形位置
|
||||
- **截图已入库**：所有 12 页截图存放于 `imgs/page_{页码}.png`
|
||||
- **截图文件命名**：`page_{物理页码}.png`（非 fig_{编号}.png），与 MD 文件中的占位符引用对齐
|
||||
|
||||
## 已知问题
|
||||
|
||||
- p237 CFSR 位域表在 PDF 原文中已存在列裂，截图辅助下有所改善但仍不完全
|
||||
- p52 文件名未使用章节号前缀（待统一）
|
||||
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|
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|
||||
来源：PM0214 Rev 10，Page 2
|
||||
|
||||
| 章节号 | 标题 | 页码 |
|
||||
|--------|------|------|
|
||||
| 1 | About this document | 12 |
|
||||
| 1.1 | Typographical conventions | 12 |
|
||||
| 1.2 | List of abbreviations for registers | 12 |
|
||||
| 1.3 | About the STM32 Cortex-M4 processor and core peripherals | 13 |
|
||||
| 1.3.1 | System level interface | 14 |
|
||||
| 1.3.2 | Integrated configurable debug | 14 |
|
||||
| 1.3.3 | Cortex-M4 processor features and benefits summary | 15 |
|
||||
| 1.3.4 | Cortex-M4 core peripherals | 16 |
|
||||
| 2 | The Cortex-M4 processor | 17 |
|
||||
| 2.1 | Programmers model | 17 |
|
||||
| 2.1.1 | Processor mode and privilege levels for software execution | 17 |
|
||||
| 2.1.2 | Stacks | 17 |
|
||||
| 2.1.3 | Core registers | 18 |
|
||||
| 2.1.4 | Exceptions and interrupts | 26 |
|
||||
| 2.1.5 | Data types | 26 |
|
||||
| 2.1.6 | The Cortex microcontroller software interface standard (CMSIS) | 26 |
|
||||
| 2.2 | Memory model | 28 |
|
||||
| 2.2.1 | Memory regions, types and attributes | 29 |
|
||||
| 2.2.2 | Memory system ordering of memory accesses | 29 |
|
||||
| 2.2.3 | Behavior of memory accesses | 30 |
|
||||
| 2.2.4 | Software ordering of memory accesses | 31 |
|
||||
| 2.2.5 | Bit-banding | 32 |
|
||||
| 2.2.6 | Memory endianness | 34 |
|
||||
| 2.2.7 | Synchronization primitives | 34 |
|
||||
| 2.2.8 | Programming hints for the synchronization primitives | 36 |
|
||||
| 2.3 | Exception model | 37 |
|
||||
| 2.3.1 | Exception states | 37 |
|
||||
| 2.3.2 | Exception types | 37 |
|
||||
| 2.3.3 | Exception handlers | 39 |
|
||||
| 2.3.4 | Vector table | 40 |
|
||||
| 2.3.5 | Exception priorities | 41 |
|
||||
| 2.3.6 | Interrupt priority grouping | 41 |
|
||||
| 2.3.7 | Exception entry and return | 42 |
|
||||
|
||||
> 原始图片：imgs/page_2.png（无图则注明无图）
|
||||
@@ -0,0 +1,48 @@
|
||||
来源：PM0214 Rev 10，Page 13
|
||||
|
||||
# 1.3 About the STM32 Cortex-M4 processor and core peripherals
|
||||
|
||||
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:
|
||||
|
||||
- Outstanding processing performance combined with fast interrupt handling
|
||||
- Enhanced system debug with extensive breakpoint and trace capabilities
|
||||
- Efficient processor core, system and memories
|
||||
- Ultra-low power consumption with integrated sleep modes
|
||||
- Platform security robustness, with integrated memory protection unit (MPU)
|
||||
|
||||
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including:
|
||||
|
||||
- IEEE754-compliant single-precision floating-point computation
|
||||
- A range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities
|
||||
- Saturating arithmetic
|
||||
- Dedicated hardware division
|
||||
|
||||
## Figure 1. STM32 Cortex-M4 implementation
|
||||
|
||||
> 架构框图展示了 Cortex-M4 处理器的内部结构，包含以下主要组件：
|
||||
|
||||
| 组件 | 说明 |
|
||||
|------|------|
|
||||
| Cortex-M4 processor | 处理器核心 |
|
||||
| FPU | 浮点运算单元 |
|
||||
| NVIC | 嵌套向量中断控制器 |
|
||||
| Memory protection unit | 内存保护单元 |
|
||||
| Debug access port | 调试访问端口 |
|
||||
| Embedded Trace Macrocell | 嵌入式跟踪宏单元 |
|
||||
| Serial wire viewer | 串行线查看器 |
|
||||
| Bus matrix | 总线矩阵 |
|
||||
| Flash patch | Flash补丁 |
|
||||
| Data watchpoints | 数据监视点 |
|
||||
| Code interface | 代码接口 |
|
||||
| SRAM and peripheral interface | SRAM和外设接口 |
|
||||
|
||||
## 寄存器位访问类型
|
||||
|
||||
| 缩写 | 含义 |
|
||||
|------|------|
|
||||
| read/clear (rc_w1) | Software can read as well as clear this bit by writing 1. Writing '0' has no effect on the bit value. |
|
||||
| read/clear (rc_w0) | Software can read as well as clear this bit by writing 0. Writing '1' has no effect on the bit value. |
|
||||
| toggle (t) | Software can only toggle this bit by writing '1'. Writing '0' has no effect. |
|
||||
| Reserved (Res.) | Reserved bit, must be kept at reset value. |
|
||||
|
||||
> 原始图片：imgs/page_13.png（无图则注明无图）
|
||||
@@ -0,0 +1,39 @@
|
||||
来源：PM0214 Rev 10，Page 12
|
||||
|
||||
# About this document
|
||||
|
||||
This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation.
|
||||
|
||||
This material is for microcontroller software and hardware engineers, including those who have no experience of Arm products.
|
||||
|
||||
This document applies to Arm®(a)-based devices.
|
||||
|
||||
## 1.1 Typographical conventions
|
||||
|
||||
The typographical conventions used in this document are:
|
||||
|
||||
## 1.2 List of abbreviations for registers
|
||||
|
||||
The following abbreviations are used in register descriptions:
|
||||
|
||||
| Abbreviation | Meaning |
|
||||
|--------------|---------|
|
||||
| read/write (rw) | Software can read and write to these bits. |
|
||||
| read-only (r) | Software can only read these bits. |
|
||||
| write-only (w) | Software can only write to this bit. Reading the bit returns the reset value. |
|
||||
|
||||
**Typographical conventions:**
|
||||
|
||||
| Style | Meaning |
|
||||
|-------|---------|
|
||||
| *italic* | Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. |
|
||||
| `<` and `>` | Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: `LDRSB<cond> <Rt>, [<Rn>, #<offset>]` |
|
||||
| **bold** | Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. |
|
||||
| `monospace` | Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. |
|
||||
| `monospace` (underlined) | Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. |
|
||||
| *monospace italic* | Denotes arguments to monospace text where the argument is to be replaced by a specific value. |
|
||||
| **`monospace bold`** | Denotes language keywords when used outside example code. |
|
||||
|
||||
> Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
|
||||
|
||||
> 原始图片：imgs/page_12.png（无图则注明无图）
|
||||
@@ -0,0 +1,45 @@
|
||||
# 2.1.3 Core registers
|
||||
|
||||
## Figure 2. Processor core registers
|
||||
|
||||
> 原始图片：imgs/page_18_fig_2.png
|
||||
|
||||
**寄存器示意图**（Figure 2）：
|
||||
- 顶部显示 **PSR**（Program Status Register，含 APSR、EPSR、IPSR 三个子寄存器）
|
||||
- 中部显示 **PRIMASK**、**FAULTMASK**、**BASEPRI**、**CONTROL** 等特殊寄存器
|
||||
- 底部显示 **SP**（含 MSP 和 PSP）、**LR**、**PC** 以及 **R0-R12** 通用寄存器
|
||||
|
||||
---
|
||||
|
||||
## Table 2. Summary of processor mode, execution privilege level, and stack usage
|
||||
|
||||
| Processor mode | Used to execute | Privilege level for software execution | Stack used |
|
||||
|----------------|-----------------|---------------------------------------|------------|
|
||||
| Thread | Applications | Privileged or unprivileged (1) | Main stack or process stack (1) |
|
||||
| Handler | Exception handlers | Always privileged | Main stack |
|
||||
|
||||
> 1. See CONTROL register on page 25.
|
||||
|
||||
---
|
||||
|
||||
## Table 3. Core register set summary
|
||||
|
||||
| Name | Type (1) | Required privilege (2) | Reset value | Description |
|
||||
|------|----------|------------------------|-------------|-------------|
|
||||
| R0-R12 | read-write | Either | Unknown | General-purpose registers on page 19 |
|
||||
| MSP | read-write | Privileged | See description | Stack pointer on page 19 |
|
||||
| PSP | read-write | Either | Unknown | Stack pointer on page 19 |
|
||||
| LR | read-write | Either | 0xFFFFFFFF | Link register on page 19 |
|
||||
| PC | read-write | Either | See description | Program counter on page 19 |
|
||||
|
||||
> 1. Type 列中的 "read-write" 表示该寄存器可被程序读写访问。
|
||||
> 2. Required privilege 列表示操作该寄存器所需的权限级别："Privileged" 仅允许特权模式，"Either" 表示特权模式和用户模式均可操作。
|
||||
|
||||
---
|
||||
|
||||
**说明**：本页面包含 3 个核心内容元素：
|
||||
1. **Figure 2** — 处理器核心寄存器示意图，展示各寄存器的层次结构与从属关系
|
||||
2. **Table 2** — 处理器模式、执行特权级、栈使用情况的概览表
|
||||
3. **Table 3** — 核心寄存器集的功能与属性汇总表
|
||||
|
||||
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 18
|
||||
@@ -0,0 +1,40 @@
|
||||
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 20
|
||||
|
||||
These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is
|
||||
shown in Figure 3 and Figure 4.
|
||||
|
||||
**Figure 3. APSR, IPSR and EPSR bit assignment**
|
||||
|
||||
|
||||
|
||||
**Figure 4. PSR bit assignment**
|
||||
|
||||
|
||||
|
||||
Access these registers individually or as a combination of any two or all three registers,
|
||||
using the register name as an argument to the MSR or MRS instructions. For example:
|
||||
- Read all of the registers using PSR with the MRS instruction.
|
||||
- Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.
|
||||
The PSR combinations and attributes are:
|
||||
|
||||
See the instruction descriptions MRS on page 186 and MSR on page 187 for more
|
||||
information about how to access the program status registers.
|
||||
|
||||
**Table 4. PSR register combinations**
|
||||
|
||||
| Register | Type | Combination |
|
||||
|----------|------|-------------|
|
||||
| PSR | read-write(1), (2) | APSR, EPSR, and IPSR |
|
||||
| IEPSR | read-only | EPSR and IPSR |
|
||||
| IAPSR | read-write(1) | APSR and IPSR |
|
||||
| EAPSR | read-write(2) | APSR and EPSR |
|
||||
|
||||
1. The processor ignores writes to the IPSR bits.
|
||||
2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
|
||||
|
||||
|25 24 23 | Reserved | ISR_NUMBER | 31 30 29 28 27 | N Z C V | 0 | Reserved |
|
||||
|----------|----------|------------|----------------|---------|---|----------|
|
||||
| 26 | Reserved | | 16 15 | ICI/IT | ICI/IT | T | Q |
|
||||
| 8 | 19 | 20 | GE[3:0] | Reserved | | |
|
||||
|
||||
> 原始图片：imgs/page_20_fig_3.png, imgs/page_20_fig_4.png
|
||||
@@ -0,0 +1,57 @@
|
||||
# 2.1.6 Usage Fault Status Register (UFSR)
|
||||
|
||||
> **寄存器名称**：Usage Fault Status Register
|
||||
> **偏移地址**：UFSR（位于 SCB 内）
|
||||
> **访问权限**：读/写（软件可写入 1 清除对应位）
|
||||
> **初始复位值**：0x0000\_0000
|
||||
> **说明**：UFSR 指示发生了何种 Usage Fault 错误。写 1 到对应位可清除该位。
|
||||
|
||||
---
|
||||
|
||||
## 位域定义
|
||||
|
||||
| 位号 | 位域名称 | 类型 | 复位值 | 描述 |
|
||||
|:----:|:--------:|:----:|:------:|:------|
|
||||
| 31:26 | Reserved | — | 0 | 保留位，必须保持清零 |
|
||||
| 25 | DIVBYZERO | RW | 0 | **Divide by zero usage fault**。当该位被置 1 时，堆栈保存的 PC 值指向执行了 SDIV 或 UDIV 指令且除数为 0 的那条指令。需通过 CCR 的 DIV\_0\_TRP 位使能除零错误捕获。0 = 无除零错误，或未使能捕获；1 = 处理器执行了除数为 0 的 SDIV/UDIV 指令 |
|
||||
| 24 | UNALIGNED | RW | 0 | **Unaligned access usage fault**。通过 CCR 的 UNALIGN\_TRP 位使能未对齐访问捕获。注意：未对齐的 LDM、STM、LDRD、STRD 指令无论 UNALIGN\_TRP 设置如何均会触发错误。0 = 无未对齐访问错误，或未使能捕获；1 = 处理器执行了未对齐内存访问 |
|
||||
| 23:20 | Reserved | — | 0 | 保留位，必须保持清零 |
|
||||
| 19 | NOCP | RW | 0 | **No coprocessor usage fault**。处理器不支持协处理器指令。0 = 未因访问协处理器而触发 usage fault；1 = 处理器尝试访问了协处理器 |
|
||||
| 18 | INVPC | RW | 0 | **Invalid PC load usage fault**（由无效的 EXC\_RETURN 加载 PC 导致）。当该位置 1 时，堆栈保存的 PC 值指向那条试图非法加载 PC 的指令。0 = 无无效 PC 加载错误；1 = 处理器尝试将非法 EXC\_RETURN 加载到 PC（因无效上下文或无效 EXC\_RETURN 值） |
|
||||
| 17 | INVSTATE | RW | 0 | **Invalid state usage fault**。当该位置 1 时，堆栈保存的 PC 值指向那条非法使用 EPSR 的指令。若某未定义指令使用了 EPSR，不会置 1。0 = 无无效状态错误；1 = 处理器尝试执行了非法使用 EPSR 的指令 |
|
||||
| 16 | UNDEFINSTR | RW | 0 | **Undefined instruction usage fault**。当该位置 1 时，堆栈保存的 PC 值指向该未定义指令。未定义指令是指处理器无法解码的指令。0 = 无未定义指令错误；1 = 处理器尝试执行了未定义指令 |
|
||||
|
||||
---
|
||||
|
||||
## 字段值摘要
|
||||
|
||||
| 位域 | = 0 | = 1 |
|
||||
|:-----|:----|:----|
|
||||
| **DIVBYZERO** | 无除零 fault，或未使能捕获 | 执行了除数为 0 的 SDIV/UDIV |
|
||||
| **UNALIGNED** | 无未对齐 fault，或未使能捕获 | 执行了未对齐内存访问 |
|
||||
| **NOCP** | 未因访问协处理器触发 fault | 尝试访问了协处理器 |
|
||||
| **INVPC** | 无无效 PC 加载 fault | 尝试非法加载 EXC\_RETURN 到 PC |
|
||||
| **INVSTATE** | 无无效状态 fault | 尝试执行了 EPSR 非法使用 |
|
||||
| **UNDEFINSTR** | 无未定义指令 fault | 尝试执行了未定义指令 |
|
||||
|
||||
---
|
||||
|
||||
## 异常返回与 PC 堆栈值
|
||||
|
||||
当 UFSR 中任意位被置 1 时，异常返回时堆栈保存的 PC 值指向**触发该 fault 的那条指令**（用于调试定位）。
|
||||
|
||||
---
|
||||
|
||||
## 相关寄存器
|
||||
|
||||
- **CCR** (Configuration and Control Register)：控制 DIV\_0\_TRP 和 UNALIGN\_TRP 位的使能（第 231 页）
|
||||
- **HFSR** (HardFault Status Register)：HardFault 状态寄存器
|
||||
- **MMFAR** (MemManage Fault Address Register)：MemManage 错误地址寄存器
|
||||
|
||||
---
|
||||
|
||||
## 设计说明
|
||||
|
||||
- UFSR 为**粘滞 sticky** 设计：写入 1 清除对应位，写入 0 保持不变
|
||||
- 所有 Reserved 位写入 1 会产生不可预测行为
|
||||
- 复位后所有位清零，表示无 Usage Fault
|
||||
@@ -0,0 +1,20 @@
|
||||
来源：PM0214 Rev 10，Page 21
|
||||
|
||||
## Application program status register
|
||||
|
||||
The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 3 on page 18 for its attributes. The bit assignment is:
|
||||
|
||||
**Table 5. APSR bit definitions**
|
||||
|
||||
| Bits | Description |
|
||||
|------|-------------|
|
||||
| Bit 31 | N: Negative or less than flag: 0: Operation result was positive, zero, greater than, or equal; 1: Operation result was negative or less than. |
|
||||
| Bit 30 | Z: Zero flag: 0: Operation result was not zero; 1: Operation result was zero. |
|
||||
| Bit 29 | C: Carry or borrow flag: 0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit; 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit. |
|
||||
| Bit 28 | V: Overflow flag: 0: Operation did not result in an overflow; 1: Operation resulted in an overflow. |
|
||||
| Bit 27 | Q: DSP overflow and saturation flag: Sticky saturation flag. 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero; 1: Indicates when an SSAT or USAT instruction results in saturation, or indicates a DSP overflow. This bit is cleared to zero by software using an MRS instruction. |
|
||||
| Bits 26:20 | Reserved. |
|
||||
| Bits 19:16 | GE[3:0]: Greater than or Equal flags. See SEL on page 105 for more information. |
|
||||
| Bits 15:0 | Reserved. |
|
||||
|
||||
> 原始图片：imgs/page_21_cover.png（无图则注明无图）
|
||||
@@ -0,0 +1,38 @@
|
||||
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 51
|
||||
|
||||
The STM32 Cortex-M4 instruction set
|
||||
|
||||
**Table 21. Cortex-M4 instructions (continued)**
|
||||
|
||||
| Mnemonic | Operands | Brief description | Flags | Page |
|
||||
|----------|----------|-------------------|-------|------|
|
||||
| AND, ANDS | {Rd,} Rn, Op2 | Logical AND | N,Z,C | 3.5.2 on page 85 |
|
||||
| ASR, ASRS | Rd, Rm, <Rs|#n> | Arithmetic shift right | N,Z,C | 3.5.3 on page 86 |
|
||||
| B | label | Branch | — | 3.9.5 on page 142 |
|
||||
| BFC | Rd, #lsb, #width | Bit field clear | — | 3.9.1 on page 139 |
|
||||
| BFI | Rd, Rn, #lsb, #width | Bit field insert | — | 3.9.1 on page 139 |
|
||||
| BIC, BICS | {Rd,} Rn, Op2 | Bit clear | N,Z,C | 3.5.2 on page 85 |
|
||||
| BKPT | #imm | Breakpoint | — | 3.11.1 on page 181 |
|
||||
| BL | label | Branch with link | — | 3.9.5 on page 142 |
|
||||
| BLX | Rm | Branch indirect with link | — | 3.9.5 on page 142 |
|
||||
| BX | Rm | Branch indirect | — | 3.9.5 on page 142 |
|
||||
| CBNZ | Rn, label | Compare and branch if non zero | — | 3.9.6 on page 144 |
|
||||
| CBZ | Rn, label | Compare and branch if zero | — | 3.9.6 on page 144 |
|
||||
| CLREX | — | Clear exclusive | — | 3.4.9 on page 80 |
|
||||
| CLZ | Rd, Rm | Count leading zeros | — | 3.5.4 on page 87 |
|
||||
| CMN | Rn, Op2 | Compare negative | N,Z,C,V | 3.5.5 on page 88 |
|
||||
| CMP | Rn, Op2 | Compare | N,Z,C,V | 3.5.5 on page 88 |
|
||||
| CPSID | iflags | Change processor state, disable interrupts | — | 3.11.2 on page 182 |
|
||||
| CPSIE | iflags | Change processor state, enable interrupts | — | 3.11.2 on page 182 |
|
||||
| DMB | — | Data memory barrier | — | 3.11.4 on page 184 |
|
||||
| DSB | — | Data synchronization barrier | — | 3.11.4 on page 184 |
|
||||
| EOR, EORS | {Rd,} Rn, Op2 | Exclusive OR | N,Z,C | 3.5.2 on page 85 |
|
||||
| ISB | — | Instruction synchronization barrier | — | 3.11.5 on page 185 |
|
||||
| IT | — | If-then condition block | — | 3.9.7 on page 145 |
|
||||
| LDM | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
|
||||
| LDMDB, LDMEA | Rn{!}, reglist | Load multiple registers, decrement before | — | 3.4.6 on page 76 |
|
||||
| LDMFD, LDMIA | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
|
||||
| LDR | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
|
||||
| LDRB, LDRBT | Rt, [Rn, #offset] | Load register with byte | — | 3.4 on page 69 |
|
||||
| LDRD | Rt, Rt2, [Rn, #offset] | Load register with two bytes | — | 3.4.2 on page 71 |
|
||||
| LDREX | Rt, [Rn, #offset] | Load register exclusive | — | 3.4.8 on page 79 |
|
||||
@@ -0,0 +1,37 @@
|
||||
来源：PM0214 Rev 10，Page 52
|
||||
|
||||
# Table 21. Cortex-M4 Instructions (continued)
|
||||
|
||||
> 指令汇总表，续前页。
|
||||
|
||||
| Mnemonic | Operands | Brief description | Flags | Page |
|
||||
|----------|----------|-------------------|-------|------|
|
||||
| LDREXB | Rt, [Rn] | Load register exclusive with byte | — | 3.4.8 on page 79 |
|
||||
| LDREXH | Rt, [Rn] | Load register exclusive with halfword | — | 3.4.8 on page 79 |
|
||||
| LDRH, LDRHT | Rt, [Rn, #offset] | Load register with halfword | — | 3.4 on page 69 |
|
||||
| LDRSB, LDRSBT | Rt, [Rn, #offset] | Load register with signed byte | — | 3.4 on page 69 |
|
||||
| LDRSH, LDRSHT | Rt, [Rn, #offset] | Load register with signed halfword | — | 3.4 on page 69 |
|
||||
| LDRT | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
|
||||
| LSL, LSLS | Rd, Rm, <Rs\|#n> | Logical shift left | N,Z,C | 3.5.3 on page 86 |
|
||||
| LSR, LSRS | Rd, Rm, <Rs\|#n> | Logical shift right | N,Z,C | 3.5.3 on page 86 |
|
||||
| MLA | Rd, Rn, Rm, Ra | Multiply with accumulate, 32-bit result | — | 3.6.1 on page 110 |
|
||||
| MLS | Rd, Rn, Rm, Ra | Multiply and subtract, 32-bit result | — | 3.6.1 on page 110 |
|
||||
| MOV, MOVS | Rd, Op2 | Move | N,Z,C | 3.5.6 on page 89 |
|
||||
| MOVT | Rd, #imm16 | Move top | — | 3.5.7 on page 91 |
|
||||
| MOVW, MOV | Rd, #imm16 | Move 16-bit constant | N,Z,C | 3.5.6 on page 89 |
|
||||
| MRS | Rd, spec_reg | Move from special register to general register | — | 3.11.6 on page 186 |
|
||||
| MSR | spec_reg, Rm | Move from general register to special register | N,Z,C,V | 3.11.7 on page 187 |
|
||||
| MUL, MULS | {Rd,} Rn, Rm | Multiply, 32-bit result | N,Z | 3.6.1 on page 110 |
|
||||
| MVN, MVNS | Rd, Op2 | Move NOT | N,Z,C | 3.5.6 on page 89 |
|
||||
| NOP | — | No operation | — | 3.11.8 on page 188 |
|
||||
| ORN, ORNS | {Rd,} Rn, Op2 | Logical OR NOT | N,Z,C | 3.5.2 on page 85 |
|
||||
| ORR, ORRS | {Rd,} Rn, Op2 | Logical OR | N,Z,C | 3.5.2 on page 85 |
|
||||
| PKHTB, PKHBT | {Rd,} Rn, Rm, Op2 | Pack Halfword | — | 3.8.1 on page 135 |
|
||||
| POP | reglist | Pop registers from stack | — | 3.4.7 on page 78 |
|
||||
| PUSH | reglist | Push registers onto stack | — | 3.4.7 on page 78 |
|
||||
| QADD | {Rd,} Rn, Rm | Saturating double and add | — | 3.7.3 on page 128 |
|
||||
| QADD16 | {Rd,} Rn, Rm | Saturating add 16 | — | 3.7.3 on page 128 |
|
||||
| QADD8 | {Rd,} Rn, Rm | Saturating add 8 | — | 3.7.3 on page 128 |
|
||||
| QASX | {Rd,} Rn, Rm | Saturating add and subtract with exchange | — | 3.7.4 on page 129 |
|
||||
|
||||
> 原始截图：imgs/page_52.png（无图则注明无图）
|
||||
@@ -0,0 +1,37 @@
|
||||
# PDF 洗 MD v3 测试结果（截图增强版）
|
||||
|
||||
**文档：** PM0214 Rev 10 - STM32 Cortex-M4 MCUs and MPUs programming manual
|
||||
**测试批次：** 12 页，覆盖封面、目录、正文、表格、代码、位域寄存器等多种页面类型
|
||||
**生成时间：** 2026-06-10
|
||||
|
||||
---
|
||||
|
||||
## 页面清单
|
||||
|
||||
| 页码 | 类型 | 输出文件 |
|
||||
|------|------|---------|
|
||||
| 1 | 封面 | page_1_cover.png（截图） |
|
||||
| 2 | 目录 | 00_目录.md |
|
||||
| 12 | About this document | 1_About_this_document_p12.md |
|
||||
| 13 | 1.3 Cortex-M4 processor | 1.3_Cortex-M4_processor_p13.md |
|
||||
| 18 | 2.1.3 Core registers + Figure 2 | 2.1.3_Core_registers_p18.md |
|
||||
| 20 | 2.1.4 Exceptions & Interrupts（双图） | 2.1.4_Exceptions_and_interrupts_p20.md |
|
||||
| 21 | 2.1 APSR bitfield | 2.1_Application_program_status_register_p21.md |
|
||||
| 51 | 3.5 Instruction summary | 3.5_Instruction_summary_p51.md |
|
||||
| 52 | 3.5 Instruction summary（续） | 3_Table21_Cortex-M4_instructions_p52.md |
|
||||
| 197 | 4.3 MPU assembly code | page_197.md |
|
||||
| 237 | 4.4.10 CFSR bitfield | page_237_cfsr.md |
|
||||
| 238 | 4.4.11 UFSR bitfield | 2.1.6_UFSR_Usage_Fault_Status_Register_p238.md |
|
||||
|
||||
---
|
||||
|
||||
## 主要变化（v3 vs v2）
|
||||
|
||||
- **截图参与决策**：每页同时输入文本 + 截图路径，模型可参照截图修正表格列裂、判断图形位置
|
||||
- **截图已入库**：所有 12 页截图存放于 `imgs/page_{页码}.png`
|
||||
- **截图文件命名**：`page_{物理页码}.png`（非 fig_{编号}.png），与 MD 文件中的占位符引用对齐
|
||||
|
||||
## 已知问题
|
||||
|
||||
- p237 CFSR 位域表在 PDF 原文中已存在列裂，截图辅助下有所改善但仍不完全
|
||||
- p52 文件名未使用章节号前缀（待统一）
|
||||
@@ -0,0 +1,74 @@
|
||||
# Page 197 — MPU Assembly Code
|
||||
|
||||
## 基本 MPU 区域配置
|
||||
|
||||
以下代码演示了基本的 MPU 区域配置过程：
|
||||
|
||||
```assembly
|
||||
; R3 = attributes
|
||||
; R4 = address
|
||||
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
|
||||
STR R1, [R0, #0x0] ; Region Number
|
||||
BIC R2, R2, #1 ; Disable
|
||||
STRH R2, [R0, #0x8] ; Region Size and Enable
|
||||
STR R4, [R0, #0x4] ; Region Base Address
|
||||
STRH R3, [R0, #0xA] ; Region Attribute
|
||||
ORR R2, #1 ; Enable
|
||||
STRH R2, [R0, #0x8] ; Region Size and Enable
|
||||
```
|
||||
|
||||
## 内存屏障指令要求
|
||||
|
||||
Software must use memory barrier instructions:
|
||||
|
||||
- **Before MPU setup**：如果存在可能受 MPU 设置更改影响的未完成内存传输（如缓冲写入），则需要在 MPU 设置前使用内存屏障指令
|
||||
- **After MPU setup**：如果 MPU 设置包含必须使用新 MPU 设置的内存传输，则需要在设置后使用内存屏障指令
|
||||
|
||||
> **注意**：如果 MPU 设置过程从异常处理程序进入，或之后跟随异常返回，则不需要内存屏障指令，因为异常入口和异常返回机制本身具有内存屏障行为。
|
||||
|
||||
由于通过 PPB（高性能总线）访问 MPU，PPB 是强序内存区域（Strongly-Ordered memory region），因此在 MPU 设置期间不需要内存屏障指令。
|
||||
|
||||
### DSB 和 ISB 指令使用
|
||||
|
||||
如果希望所有内存访问行为在编程序列后立即生效，需要使用 DSB 和 ISB 指令：
|
||||
|
||||
- **DSB**：在更改 MPU 设置后需要（如上下文切换结束时）
|
||||
- **ISB**：如果编程 MPU 区域的代码通过分支或调用进入时需要；如果通过异常返回进入或触发异常，则不需要 ISB
|
||||
|
||||
## 多字写入更新 MPU 区域
|
||||
|
||||
### 逐字编程方式
|
||||
|
||||
```assembly
|
||||
; R1 = region number
|
||||
; R2 = address
|
||||
; R3 = size, attributes in one
|
||||
LDR R0, =MPU_RNR
|
||||
; 0xE000ED98, MPU region number register
|
||||
STR R1, [R0, #0x0]
|
||||
; Region Number
|
||||
STR R2, [R0, #0x4]
|
||||
; Region Base Address
|
||||
STR R3, [R0, #0x8]
|
||||
; Region Attribute, Size and Enable
|
||||
```
|
||||
|
||||
### 使用 STM 指令优化
|
||||
|
||||
```assembly
|
||||
; R1 = region number
|
||||
; R2 = address
|
||||
; R3 = size, attributes in one
|
||||
LDR R0, =MPU_RNR
|
||||
; 0xE000ED98, MPU region number register
|
||||
STM R0, {R1-R3}
|
||||
; Region Number, address, attribute, size and enable
|
||||
```
|
||||
|
||||
## 使用 RBAR 预打包信息
|
||||
|
||||
可以使用两个 word 完成预打包信息的编程。此时 RBAR 包含所需的区域号，且 VALID 位设置为 1。
|
||||
|
||||
参见 **MPU region base address register (MPU_RBAR)**（第 203 页）。
|
||||
|
||||
适用于数据静态打包的场景，例如 bootloader。
|
||||
@@ -0,0 +1,68 @@
|
||||
# 4.4.10 Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)
|
||||
|
||||
**Address offset:** `0x28`
|
||||
**Reset value:** `0x0000 0000`
|
||||
**Required privilege:** Privileged
|
||||
|
||||
The CFSR is byte-accessible and indicates the cause of a memory management fault, bus fault, or usage fault.
|
||||
|
||||
## CFSR subregisters
|
||||
|
||||
| Subregister | Address | Access |
|
||||
|-------------|----------|--------|
|
||||
| MMFSR | Bits[7:0] | Byte access at `0xE000ED28` |
|
||||
| BFSR | Bits[15:8] | Byte access at `0xE000ED29` |
|
||||
| UFSR | Bits[31:16] | Halfword access at `0xE000ED2A` |
|
||||
| Full CFSR | Bits[31:0] | Word access at `0xE000ED28` |
|
||||
|
||||
## Bitfield definitions
|
||||
|
||||
### UFSR — Usage Fault Status Register (Bits[31:16])
|
||||
|
||||
| Bit | Field | Type | Description |
|
||||
|-----|-------|------|-------------|
|
||||
| 31 | DIVBY | rc_w1 | Divide by zero trap |
|
||||
| 30 | ZERO | rc_w1 | Unaligned memory access trap |
|
||||
| 29 | UNALI | rc_w1 | Unaligned access fault |
|
||||
| 28 | UNALIGNED | rc_w1 | Unaligned memory access fault |
|
||||
| 27 | Reserved | - | - |
|
||||
| 26 | NOCP | rc_w1 | No coprocessor fault |
|
||||
| 25 | INVPC | rc_w1 | Invalid PC load fault |
|
||||
| 24 | INVSTATE | rc_w1 | Invalid state fault |
|
||||
| 23 | UNDEF | rc_w1 | Undefined instruction fault |
|
||||
| 22 | Reserved | - | - |
|
||||
| 21 | INSTR | rc_w1 | Instruction access fault |
|
||||
|
||||
### BFSR — Bus Fault Status Register (Bits[15:8])
|
||||
|
||||
| Bit | Field | Type | Description |
|
||||
|-----|-------|------|-------------|
|
||||
| 15 | BFARVALID | rc_w1 | Bus Fault Address Register valid |
|
||||
| 14 | Reserved | - | - |
|
||||
| 13 | LSPERR | rw | Lazy save error |
|
||||
| 12 | STKERR | rw | Stack error |
|
||||
| 11 | UNSTKERR | rw | Unstack error |
|
||||
| 10 | IMPRECISERR | rw | Imprecise data access error |
|
||||
| 9 | PRECISERR | rw | Precise data access error |
|
||||
| 8 | IBUSERR | rw | Instruction bus error |
|
||||
|
||||
### MMFSR — Memory Management Fault Status Register (Bits[7:0])
|
||||
|
||||
| Bit | Field | Type | Description |
|
||||
|-----|-------|------|-------------|
|
||||
| 7 | MMARVALID | rc_w1 | Memory Management Fault Address Register valid |
|
||||
| 6 | Reserved | - | - |
|
||||
| 5 | MLSPERR | rw | Lazy save error (memory management) |
|
||||
| 4 | MSTKERR | rw | Stack error (memory management) |
|
||||
| 3 | MUNSTKERR | rw | Unstack error (memory management) |
|
||||
| 2 | Reserved | - | - |
|
||||
| 1 | DACCVIOL | rw | Data access violation |
|
||||
| 0 | IACCVIOL | rw | Instruction access violation |
|
||||
|
||||
---
|
||||
|
||||
## See also
|
||||
|
||||
- Usage fault status register (UFSR) — page 238
|
||||
- Bus fault status register (BFSR) — page 239
|
||||
- Memory management fault address register (MMFSR) — page 240
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
# Page 197 — MPU Assembly Code
|
||||
|
||||
## 基本 MPU 区域配置
|
||||
|
||||
以下代码演示了基本的 MPU 区域配置过程：
|
||||
|
||||
```assembly
|
||||
; R3 = attributes
|
||||
; R4 = address
|
||||
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
|
||||
STR R1, [R0, #0x0] ; Region Number
|
||||
BIC R2, R2, #1 ; Disable
|
||||
STRH R2, [R0, #0x8] ; Region Size and Enable
|
||||
STR R4, [R0, #0x4] ; Region Base Address
|
||||
STRH R3, [R0, #0xA] ; Region Attribute
|
||||
ORR R2, #1 ; Enable
|
||||
STRH R2, [R0, #0x8] ; Region Size and Enable
|
||||
```
|
||||
|
||||
## 内存屏障指令要求
|
||||
|
||||
Software must use memory barrier instructions:
|
||||
|
||||
- **Before MPU setup**：如果存在可能受 MPU 设置更改影响的未完成内存传输（如缓冲写入），则需要在 MPU 设置前使用内存屏障指令
|
||||
- **After MPU setup**：如果 MPU 设置包含必须使用新 MPU 设置的内存传输，则需要在设置后使用内存屏障指令
|
||||
|
||||
> **注意**：如果 MPU 设置过程从异常处理程序进入，或之后跟随异常返回，则不需要内存屏障指令，因为异常入口和异常返回机制本身具有内存屏障行为。
|
||||
|
||||
由于通过 PPB（高性能总线）访问 MPU，PPB 是强序内存区域（Strongly-Ordered memory region），因此在 MPU 设置期间不需要内存屏障指令。
|
||||
|
||||
### DSB 和 ISB 指令使用
|
||||
|
||||
如果希望所有内存访问行为在编程序列后立即生效，需要使用 DSB 和 ISB 指令：
|
||||
|
||||
- **DSB**：在更改 MPU 设置后需要（如上下文切换结束时）
|
||||
- **ISB**：如果编程 MPU 区域的代码通过分支或调用进入时需要；如果通过异常返回进入或触发异常，则不需要 ISB
|
||||
|
||||
## 多字写入更新 MPU 区域
|
||||
|
||||
### 逐字编程方式
|
||||
|
||||
```assembly
|
||||
; R1 = region number
|
||||
; R2 = address
|
||||
; R3 = size, attributes in one
|
||||
LDR R0, =MPU_RNR
|
||||
; 0xE000ED98, MPU region number register
|
||||
STR R1, [R0, #0x0]
|
||||
; Region Number
|
||||
STR R2, [R0, #0x4]
|
||||
; Region Base Address
|
||||
STR R3, [R0, #0x8]
|
||||
; Region Attribute, Size and Enable
|
||||
```
|
||||
|
||||
### 使用 STM 指令优化
|
||||
|
||||
```assembly
|
||||
; R1 = region number
|
||||
; R2 = address
|
||||
; R3 = size, attributes in one
|
||||
LDR R0, =MPU_RNR
|
||||
; 0xE000ED98, MPU region number register
|
||||
STM R0, {R1-R3}
|
||||
; Region Number, address, attribute, size and enable
|
||||
```
|
||||
|
||||
## 使用 RBAR 预打包信息
|
||||
|
||||
可以使用两个 word 完成预打包信息的编程。此时 RBAR 包含所需的区域号，且 VALID 位设置为 1。
|
||||
|
||||
参见 **MPU region base address register (MPU_RBAR)**（第 203 页）。
|
||||
|
||||
适用于数据静态打包的场景，例如 bootloader。
|
||||
@@ -0,0 +1,68 @@
|
||||
# 4.4.10 Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)
|
||||
|
||||
**Address offset:** `0x28`
|
||||
**Reset value:** `0x0000 0000`
|
||||
**Required privilege:** Privileged
|
||||
|
||||
The CFSR is byte-accessible and indicates the cause of a memory management fault, bus fault, or usage fault.
|
||||
|
||||
## CFSR subregisters
|
||||
|
||||
| Subregister | Address | Access |
|
||||
|-------------|----------|--------|
|
||||
| MMFSR | Bits[7:0] | Byte access at `0xE000ED28` |
|
||||
| BFSR | Bits[15:8] | Byte access at `0xE000ED29` |
|
||||
| UFSR | Bits[31:16] | Halfword access at `0xE000ED2A` |
|
||||
| Full CFSR | Bits[31:0] | Word access at `0xE000ED28` |
|
||||
|
||||
## Bitfield definitions
|
||||
|
||||
### UFSR — Usage Fault Status Register (Bits[31:16])
|
||||
|
||||
| Bit | Field | Type | Description |
|
||||
|-----|-------|------|-------------|
|
||||
| 31 | DIVBY | rc_w1 | Divide by zero trap |
|
||||
| 30 | ZERO | rc_w1 | Unaligned memory access trap |
|
||||
| 29 | UNALI | rc_w1 | Unaligned access fault |
|
||||
| 28 | UNALIGNED | rc_w1 | Unaligned memory access fault |
|
||||
| 27 | Reserved | - | - |
|
||||
| 26 | NOCP | rc_w1 | No coprocessor fault |
|
||||
| 25 | INVPC | rc_w1 | Invalid PC load fault |
|
||||
| 24 | INVSTATE | rc_w1 | Invalid state fault |
|
||||
| 23 | UNDEF | rc_w1 | Undefined instruction fault |
|
||||
| 22 | Reserved | - | - |
|
||||
| 21 | INSTR | rc_w1 | Instruction access fault |
|
||||
|
||||
### BFSR — Bus Fault Status Register (Bits[15:8])
|
||||
|
||||
| Bit | Field | Type | Description |
|
||||
|-----|-------|------|-------------|
|
||||
| 15 | BFARVALID | rc_w1 | Bus Fault Address Register valid |
|
||||
| 14 | Reserved | - | - |
|
||||
| 13 | LSPERR | rw | Lazy save error |
|
||||
| 12 | STKERR | rw | Stack error |
|
||||
| 11 | UNSTKERR | rw | Unstack error |
|
||||
| 10 | IMPRECISERR | rw | Imprecise data access error |
|
||||
| 9 | PRECISERR | rw | Precise data access error |
|
||||
| 8 | IBUSERR | rw | Instruction bus error |
|
||||
|
||||
### MMFSR — Memory Management Fault Status Register (Bits[7:0])
|
||||
|
||||
| Bit | Field | Type | Description |
|
||||
|-----|-------|------|-------------|
|
||||
| 7 | MMARVALID | rc_w1 | Memory Management Fault Address Register valid |
|
||||
| 6 | Reserved | - | - |
|
||||
| 5 | MLSPERR | rw | Lazy save error (memory management) |
|
||||
| 4 | MSTKERR | rw | Stack error (memory management) |
|
||||
| 3 | MUNSTKERR | rw | Unstack error (memory management) |
|
||||
| 2 | Reserved | - | - |
|
||||
| 1 | DACCVIOL | rw | Data access violation |
|
||||
| 0 | IACCVIOL | rw | Instruction access violation |
|
||||
|
||||
---
|
||||
|
||||
## See also
|
||||
|
||||
- Usage fault status register (UFSR) — page 238
|
||||
- Bus fault status register (BFSR) — page 239
|
||||
- Memory management fault address register (MMFSR) — page 240
|
||||
Reference in New Issue
Block a user