来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 51

The STM32 Cortex-M4 instruction set

**Table 21. Cortex-M4 instructions (continued)**

| Mnemonic | Operands | Brief description | Flags | Page |
|----------|----------|-------------------|-------|------|
| AND, ANDS | {Rd,} Rn, Op2 | Logical AND | N,Z,C | 3.5.2 on page 85 |
| ASR, ASRS | Rd, Rm, <Rs\|#n> | Arithmetic shift right | N,Z,C | 3.5.3 on page 86 |
| B | label | Branch | — | 3.9.5 on page 142 |
| BFC | Rd, #lsb, #width | Bit field clear | — | 3.9.1 on page 139 |
| BFI | Rd, Rn, #lsb, #width | Bit field insert | — | 3.9.1 on page 139 |
| BIC, BICS | {Rd,} Rn, Op2 | Bit clear | N,Z,C | 3.5.2 on page 85 |
| BKPT | #imm | Breakpoint | — | 3.11.1 on page 181 |
| BL | label | Branch with link | — | 3.9.5 on page 142 |
| BLX | Rm | Branch indirect with link | — | 3.9.5 on page 142 |
| BX | Rm | Branch indirect | — | 3.9.5 on page 142 |
| CBNZ | Rn, label | Compare and branch if non zero | — | 3.9.6 on page 144 |
| CBZ | Rn, label | Compare and branch if zero | — | 3.9.6 on page 144 |
| CLREX | — | Clear exclusive | — | 3.4.9 on page 80 |
| CLZ | Rd, Rm | Count leading zeros | — | 3.5.4 on page 87 |
| CMN | Rn, Op2 | Compare negative | N,Z,C,V | 3.5.5 on page 88 |
| CMP | Rn, Op2 | Compare | N,Z,C,V | 3.5.5 on page 88 |
| CPSID | iflags | Change processor state, disable interrupts | — | 3.11.2 on page 182 |
| CPSIE | iflags | Change processor state, enable interrupts | — | 3.11.2 on page 182 |
| DMB | — | Data memory barrier | — | 3.11.4 on page 184 |
| DSB | — | Data synchronization barrier | — | 3.11.4 on page 184 |
| EOR, EORS | {Rd,} Rn, Op2 | Exclusive OR | N,Z,C | 3.5.2 on page 85 |
| ISB | — | Instruction synchronization barrier | — | 3.11.5 on page 185 |
| IT | — | If-then condition block | — | 3.9.7 on page 145 |
| LDM | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
| LDMDB, LDMEA | Rn{!}, reglist | Load multiple registers, decrement before | — | 3.4.6 on page 76 |
| LDMFD, LDMIA | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
| LDR | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
| LDRB, LDRBT | Rt, [Rn, #offset] | Load register with byte | — | 3.4 on page 69 |
| LDRD | Rt, Rt2, [Rn, #offset] | Load register with two bytes | — | 3.4.2 on page 71 |
| LDREX | Rt, [Rn, #offset] | Load register exclusive | — | 3.4.8 on page 79 |
| LDRH, LDRHT | Rt, [Rn, #offset] | Load register with halfword | — | 3.4 on page 69 |
| LDRSB, LDRSBT | Rt, [Rn, #offset] | Load register with signed byte | — | 3.4 on page 69 |
| LDRSH, LDRSHT | Rt, [Rn, #offset] | Load register with signed halfword | — | 3.4 on page 69 |
| LDRT | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
| LSL, LSLS | Rd, Rm, <Rs\|#n> | Logical shift left | N,Z,C | 3.5.3 on page 86 |
| LSR, LSRS | Rd, Rm, <Rs\|#n> | Logical shift right | N,Z,C | 3.5.3 on page 86 |
| MLA | Rd, Rn, Rm, Ra | Multiply with accumulate, 32-bit result | — | 3.6.1 on page 110 |
| MLS | Rd, Rn, Rm, Ra | Multiply and subtract, 32-bit result | — | 3.6.1 on page 110 |
| MOV, MOVS | Rd, Op2 | Move | N,Z,C | 3.5.6 on page 89 |
| MOVT | Rd, #imm16 | Move top | — | 3.5.7 on page 91 |
| MOVW, MOV | Rd, #imm16 | Move 16-bit constant | N,Z,C | 3.5.6 on page 89 |
| MRS | Rd, spec_reg | Move from special register to general register | — | 3.11.6 on page 186 |
| MSR | spec_reg, Rm | Move from general register to special register | N,Z,C,V | 3.11.7 on page 187 |
| MUL, MULS | {Rd,} Rn, Rm | Multiply, 32-bit result | N,Z | 3.6.1 on page 110 |
| MVN, MVNS | Rd, Op2 | Move NOT | N,Z,C | 3.5.6 on page 89 |
| NOP | — | No operation | — | 3.11.8 on page 188 |
| ORN, ORNS | {Rd,} Rn, Op2 | Logical OR NOT | N,Z,C | 3.5.2 on page 85 |
| ORR, ORRS | {Rd,} Rn, Op2 | Logical OR | N,Z,C | 3.5.2 on page 85 |
| PKHTB, PKHBT | {Rd,} Rn, Rm, Op2 | Pack Halfword | — | 3.8.1 on page 135 |
| POP | reglist | Pop registers from stack | — | 3.4.7 on page 78 |
| PUSH | reglist | Push registers onto stack | — | 3.4.7 on page 78 |
| QADD | {Rd,} Rn, Rm | Saturating double and add | — | 3.7.3 on page 128 |
| QADD16 | {Rd,} Rn, Rm | Saturating add 16 | — | 3.7.3 on page 128 |
| QADD8 | {Rd,} Rn, Rm | Saturating add 8 | — | 3.7.3 on page 128 |
| QASX | {Rd,} Rn, Rm | Saturating add and subtract with exchange | — | 3.7.4 on page 129 |

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