hwd32
a0549647dc
新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
1.5 KiB
1.5 KiB
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 21
Application program status register
The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 3 on page 18 for its attributes. The bit assignment is:
Table 5. APSR bit definitions
| Bits | Description |
|---|---|
| Bit 31 | N: Negative or less than flag: 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than. |
| Bit 30 | Z: Zero flag: 0: Operation result was not zero 1: Operation result was zero. |
| Bit 29 | C: Carry or borrow flag: 0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit. |
| Bit 28 | V: Overflow flag: 0: Operation did not result in an overflow 1: Operation resulted in an overflow. |
| Bit 27 | Q: DSP overflow and saturation flag: Sticky saturation flag. 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1: Indicates when an SSAT or USAT instruction results in saturation, or indicates a DSP overflow. This bit is cleared to zero by software using an MRS instruction. |
| Bits 26:20 | Reserved. |
| Bits 19:16 | GE[3:0]: Greater than or Equal flags. See SEL on page 105 for more information. |
| Bits 15:0 | Reserved. |
原始图片：imgs/page_21_*.png（无图则注明无图）