hwd32
99c793e065
- source/: PyMuPDF 提取的原始文本（p1/p2/p12/p13/p51/p52） - output/: v5提示词处理后的Markdown结果 - output/imgs/: 封面占位符 Co-Authored-By: Claude <noreply@anthropic.com>
169 lines
2.0 KiB
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169 lines
2.0 KiB
Plaintext
PM0214 Rev 10
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51/262
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PM0214
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The STM32 Cortex-M4 instruction set
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261
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AND, ANDS
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{Rd,} Rn, Op2
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Logical AND
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N,Z,C
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3.5.2 on page 85
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ASR, ASRS
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Rd, Rm, <Rs|#n>
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Arithmetic shift right
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N,Z,C
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3.5.3 on page 86
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B
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label
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Branch
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—
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3.9.5 on page 142
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BFC
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Rd, #lsb, #width
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Bit field clear
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—
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3.9.1 on page 139
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BFI
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Rd, Rn, #lsb, #width
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Bit field insert
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—
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3.9.1 on page 139
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BIC, BICS
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{Rd,} Rn, Op2
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Bit clear
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N,Z,C
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3.5.2 on page 85
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BKPT
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#imm
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Breakpoint
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—
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3.11.1 on page 181
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BL
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label
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Branch with link
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—
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3.9.5 on page 142
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BLX
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Rm
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Branch indirect with link
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—
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3.9.5 on page 142
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BX
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Rm
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Branch indirect
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—
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3.9.5 on page 142
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CBNZ
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Rn, label
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Compare and branch if non
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zero
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—
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3.9.6 on page 144
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CBZ
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Rn, label
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Compare and branch if zero
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—
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3.9.6 on page 144
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CLREX
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—
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Clear exclusive
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—
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3.4.9 on page 80
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CLZ
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Rd, Rm
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Count leading zeros
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—
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3.5.4 on page 87
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CMN
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Rn, Op2
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Compare negative
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N,Z,C,V 3.5.5 on page 88
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CMP
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Rn, Op2
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Compare
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N,Z,C,V 3.5.5 on page 88
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CPSID
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iflags
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Change processor state,
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disable interrupts
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—
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3.11.2 on page 182
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CPSIE
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iflags
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Change processor state,
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enable interrupts
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—
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3.11.2 on page 182
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DMB
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—
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Data memory barrier
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—
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3.11.4 on page 184
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DSB
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—
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Data synchronization barrier
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—
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3.11.4 on page 184
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EOR, EORS
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{Rd,} Rn, Op2
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Exclusive OR
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N,Z,C
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3.5.2 on page 85
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ISB
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—
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Instruction synchronization
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barrier
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—
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3.11.5 on page 185
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IT
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—
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If-then condition block
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—
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3.9.7 on page 145
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LDM
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Rn{!}, reglist
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Load multiple registers,
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increment after
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—
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3.4.6 on page 76
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LDMDB,
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LDMEA
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Rn{!}, reglist
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Load multiple registers,
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decrement before
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—
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3.4.6 on page 76
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LDMFD,
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LDMIA
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Rn{!}, reglist
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Load multiple registers,
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increment after
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—
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3.4.6 on page 76
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LDR
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Rt, [Rn, #offset]
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Load register with word
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—
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3.4 on page 69
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LDRB,
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LDRBT
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Rt, [Rn, #offset]
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Load register with byte
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—
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3.4 on page 69
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LDRD
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Rt, Rt2, [Rn, #offset]
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Load register with two bytes
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—
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3.4.2 on page 71
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LDREX
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Rt, [Rn, #offset]
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Load register exclusive
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—
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3.4.8 on page 79
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Table 21. Cortex-M4 instructions (continued)
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Mnemonic
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Operands
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Brief description
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Flags
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Page |