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新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
43 lines
1.6 KiB
Markdown
43 lines
1.6 KiB
Markdown
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 20
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These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is
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shown in Figure 3 and Figure 4.
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**Figure 3. APSR, IPSR and EPSR bit assignment**
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**Figure 4. PSR bit assignment**
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Access these registers individually or as a combination of any two or all three registers,
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using the register name as an argument to the MSR or MRS instructions. For example:
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•
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Read all of the registers using PSR with the MRS instruction.
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•
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Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.
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The PSR combinations and attributes are:
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See the instruction descriptions MRS on page 186 and MSR on page 187 for more
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information about how to access the program status registers.
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**Table 4. PSR register combinations**
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| Register | Type | Combination |
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|----------|------|-------------|
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| PSR | read-write(1), (2) | APSR, EPSR, and IPSR |
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| IEPSR | read-only | EPSR and IPSR |
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| IAPSR | read-write(1) | APSR and IPSR |
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| EAPSR | read-write(2) | APSR and EPSR |
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1. The processor ignores writes to the IPSR bits.
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2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
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| 25 24 23 | Reserved | ISR_NUMBER | 31 30 29 28 27 | N Z C V | 0 | Reserved |
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|----------|----------|------------|----------------|---------|---|----------|
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| 26 | Reserved | | 16 15 | ICI/IT | ICI/IT | T | Q |
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| 8 | 19 | 20 | GE[3:0] | Reserved | | |
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> 原始图片：imgs/page_20_fig_3.png, imgs/page_20_fig_4.png
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