hwd32
a0549647dc
新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
151 lines
1.7 KiB
Markdown
151 lines
1.7 KiB
Markdown
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 237
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4.4.10
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Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)
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Address offset: 0x28
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Reset value: 0x0000 0000
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Required privilege: Privileged
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The following subsections describe the subregisters that make up the CFSR:
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•
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Usage fault status register (UFSR) on page 238
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•
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Bus fault status register (BFSR) on page 239
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•
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Memory management fault address register (MMFSR) on page 240
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The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
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•
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Access the complete CFSR with a word access to 0xE000ED28
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•
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Access the MMFSR with a byte access to 0xE000ED28
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•
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Access the MMFSR and BFSR with a halfword access to 0xE000ED28
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•
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Access the BFSR with a byte access to 0xE000ED29
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•
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Access the UFSR with a halfword access to 0xE000ED2A.
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The CFSR indicates the cause of a memory management fault, bus fault, or usage fault.
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**Figure 20. CFSR subregisters**
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Memory Management
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Fault Status Register
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31
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16 15
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8
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7
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0
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Usage Fault Status Register
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Bus Fault Status
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Register
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UFSR
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BFSR
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MMFSR
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31
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30
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29
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28
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27
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26
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25
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24
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23
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22
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21
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20
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19
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18
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17
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16
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Reserved
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DIVBY
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ZERO
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UNALI
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GNED
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Reserved
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NOCP
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INVPC
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INV
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STATE
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UNDEF
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INSTR
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rc_w1
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rc_w1
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rc_w1
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rc_w1
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rc_w1
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rc_w1
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15
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14
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13
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12
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11
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10
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9
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8
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7
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6
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5
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4
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3
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2
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1
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0
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BFARV
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ALID
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Reserv
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ed
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LSP
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ERR
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STK
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ERR
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UNSTK
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ERR
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IMPRE
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CIS
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ERR
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PRECI
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S ERR
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IBUS
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ERR
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MMAR
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VALID
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Reserv
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ed
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MLSP
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ERR
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MSTK
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ERR
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M
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UNSTK
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ERR
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Res.
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DACC
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VIOL
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IACC
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VIOL
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rw
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rw
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rw
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rw
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rw
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rw
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rw
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rw
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rw
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rw
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rw
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rw
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rw
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Bits 31:16 UFSR: see Usage fault status register (UFSR) on page 238
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Bits 15:8 BFSR: see Bus fault status register (BFSR) on page 239
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Bits 7:0 MMFSR: see Memory management fault address register (MMFSR) on page 240
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> 原始图片：imgs/page_237_fig_20.png
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