hwd32
a0549647dc
新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
63 lines
1.8 KiB
Plaintext
63 lines
1.8 KiB
Plaintext
PM0214 Rev 10
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13/262
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PM0214
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About this document
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261
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1.3
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About the STM32 Cortex-M4 processor and core peripherals
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The Cortex-M4 processor is a high performance 32-bit processor designed for the
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microcontroller market. It offers significant benefits to developers, including:
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•
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outstanding processing performance combined with fast interrupt handling
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•
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enhanced system debug with extensive breakpoint and trace capabilities
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•
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efficient processor core, system and memories
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•
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ultra-low power consumption with integrated sleep modes
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•
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platform security robustness, with integrated memory protection unit (MPU).
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The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage
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pipeline Harvard architecture, making it ideal for demanding embedded applications. The
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processor delivers exceptional power efficiency through an efficient instruction set and
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extensively optimized design, providing high-end processing hardware including IEEE754-
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compliant single-precision floating-point computation, a range of single-cycle and SIMD
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multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated
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hardware division.
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Figure 1. STM32 Cortex-M4 implementation
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read/clear (rc_w1)
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Software can read as well as clear this bit by writing 1.
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Writing ‘0’ has no effect on the bit value.
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read/clear (rc_w0)
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Software can read as well as clear this bit by writing 0.
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Writing ‘1’ has no effect on the bit value.
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toggle (t)
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Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.
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Reserved (Res.)
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Reserved bit, must be kept at reset value.
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Embedded
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Trace Macrocell
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NVIC
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Debug
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access
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port
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Memory
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protection unit
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Serial
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wire
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viewer
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Bus matrix
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Code
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interface
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SRAM and
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peripheral interface
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Data
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watchpoints
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Flash
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patch
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Cortex-M4
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processor
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FPU
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Processor
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core
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