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新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
45 lines
1.3 KiB
Plaintext
45 lines
1.3 KiB
Plaintext
PM0214 Rev 10
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21/262
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PM0214
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The Cortex-M4 processor
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261
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Application program status register
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The APSR contains the current state of the condition flags from previous instruction
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executions. See the register summary in Table 3 on page 18 for its attributes. The bit
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assignment is:
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Table 5. APSR bit definitions
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Bits
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Description
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Bit 31
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N: Negative or less than flag:
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0: Operation result was positive, zero, greater than, or equal
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1: Operation result was negative or less than.
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Bit 30
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Z: Zero flag:
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0: Operation result was not zero
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1: Operation result was zero.
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Bit 29
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C: Carry or borrow flag:
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0: Add operation did not result in a carry bit or subtract operation resulted in a
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borrow bit
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1: Add operation resulted in a carry bit or subtract operation did not result in a
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borrow bit.
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Bit 28
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V: Overflow flag:
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0: Operation did not result in an overflow
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1: Operation resulted in an overflow.
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Bit 27
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Q: DSP overflow and saturation flag: Sticky saturation flag.
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0: Indicates that saturation has not occurred since reset or since the bit was last
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cleared to zero
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1: Indicates when an SSAT or USAT instruction results in saturation, or indicates a
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DSP overflow.
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This bit is cleared to zero by software using an MRS instruction.
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Bits 26:20
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Reserved.
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Bits 19:16
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GE[3:0]: Greater than or Equal flags. See SEL on page 105 for more information.
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Bits 15:0
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Reserved.
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